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path: root/src/verilog/Value.v
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* Fixes to make develop compileYann Herklotz2020-06-241-5/+3
* More to proofYann Herklotz2020-06-231-7/+9
* Admit the value proofYann Herklotz2020-06-221-3/+5
* Merge branch 'arrays-proof' into developYann Herklotz2020-06-221-0/+5
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| * Finish structure of Aindexed2scaled ILoad proof.James Pollard2020-06-201-0/+5
* | Add proof of nat equivYann Herklotz2020-06-201-2/+15
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* Working on proof.James Pollard2020-06-111-0/+5
* Uncomment proofYann Herklotz2020-06-031-0/+5
* Add proof for equivalence of movYann Herklotz2020-06-021-2/+33
* Add more proofs and remove AdmittedYann Herklotz2020-05-271-8/+14
* Fix definitions in Value and add lemmasYann Herklotz2020-05-201-7/+35
* Add lessdef for valuesYann Herklotz2020-05-081-3/+10
* Use associations instead of stateYann Herklotz2020-05-071-0/+4
* Add changes to valueYann Herklotz2020-05-061-2/+9
* Simplifications to proofYann Herklotz2020-05-051-2/+0
* Finish manual simulationYann Herklotz2020-05-051-4/+25
* Add equality check for valueYann Herklotz2020-05-041-15/+21
* Refine the semanticsYann Herklotz2020-05-041-8/+36
* Add hex notation to valuesYann Herklotz2020-05-031-0/+9
* Add valueToInt functionYann Herklotz2020-04-241-0/+3
* Remove unnecessary LemmaYann Herklotz2020-04-221-8/+1
* Add main module runYann Herklotz2020-04-171-1/+1
* Create Value module for bitvectorsYann Herklotz2020-04-151-0/+217