Commit message (Expand) | Author | Age | Files | Lines | |
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* | Add more unproven instructions, Admitted equiv to spec | Yann Herklotz | 2020-06-14 | 1 | -1/+3 |
* | Generate Verilog from HTL | Yann Herklotz | 2020-06-12 | 1 | -69/+114 |
* | Merge branch 'develop' into arrays-proof | James Pollard | 2020-06-09 | 1 | -6/+3 |
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| * | Finished main proof with small assumptions | Yann Herklotz | 2020-06-04 | 1 | -6/+3 |
* | | Update HTL semantics to support arrays. | James Pollard | 2020-06-02 | 1 | -5/+7 |
* | | Paramterise associations type to avoid some duplication. | James Pollard | 2020-06-02 | 1 | -44/+40 |
* | | First draft of array semantics. | James Pollard | 2020-06-01 | 1 | -112/+188 |
* | | Merge branch 'develop' into arrays-proof | James Pollard | 2020-05-30 | 1 | -88/+247 |
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| * | Fix compilation moving to PTree | Yann Herklotz | 2020-05-29 | 1 | -7/+7 |
| * | Switch position of empty rule | Yann Herklotz | 2020-05-20 | 1 | -4/+4 |
| * | Add AssocMap | Yann Herklotz | 2020-05-08 | 1 | -39/+25 |
| * | Use associations instead of state | Yann Herklotz | 2020-05-07 | 1 | -70/+65 |
| * | Rename assoclist to assocset | Yann Herklotz | 2020-05-07 | 1 | -25/+25 |
| * | Minimised manual simulation | Yann Herklotz | 2020-05-05 | 1 | -10/+10 |
| * | Simplifications to proof | Yann Herklotz | 2020-05-05 | 1 | -2/+8 |
| * | Add equality check for value | Yann Herklotz | 2020-05-04 | 1 | -1/+1 |
| * | Refine the semantics | Yann Herklotz | 2020-05-04 | 1 | -42/+63 |
| * | Change to State | Yann Herklotz | 2020-05-03 | 1 | -21/+22 |
| * | Add CompCert semantics for Verilog | Yann Herklotz | 2020-04-24 | 1 | -81/+152 |
| * | Add stmnt_runp inductive | Yann Herklotz | 2020-04-22 | 1 | -27/+106 |
* | | (Tentatively) working stack array/memory support. | James Pollard | 2020-05-26 | 1 | -0/+4 |
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* | Use State in semantics instead of splitting it up | Yann Herklotz | 2020-04-22 | 1 | -95/+98 |
* | Fix Verilog.v | Yann Herklotz | 2020-04-17 | 1 | -1/+1 |
* | Add main module run | Yann Herklotz | 2020-04-17 | 1 | -50/+78 |
* | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 |
* | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -7/+8 |
* | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -5/+36 |
* | Add documentation and fix makefile for Compcert | Yann Herklotz | 2020-03-31 | 1 | -1/+1 |
* | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -3/+10 |
* | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 1 | -1/+4 |
* | Change Verilog AST back to more traditional AST | Yann Herklotz | 2020-03-29 | 1 | -30/+44 |
* | Update AST and value representations | Yann Herklotz | 2020-03-29 | 1 | -213/+42 |
* | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 1 | -0/+253 |