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* Add Verilog semantics with new Verilog moduleYann Herklotz2020-04-151-33/+326
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* Handle loops and conditionals correctlyYann Herklotz2020-04-021-7/+8
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* Update compilationYann Herklotz2020-04-011-5/+36
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* Add documentation and fix makefile for CompcertYann Herklotz2020-03-311-1/+1
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* Add more operators and print themYann Herklotz2020-03-311-3/+10
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* Improve Verilog error messagesYann Herklotz2020-03-311-1/+4
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* Change Verilog AST back to more traditional ASTYann Herklotz2020-03-291-30/+44
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* Update AST and value representationsYann Herklotz2020-03-291-213/+42
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* Rename Verilog AST filesYann Herklotz2020-03-291-0/+253