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* Remove Test.vYann Herklotz2020-06-121-99/+0
* Generate Verilog from HTLYann Herklotz2020-06-121-69/+114
* Merge branch 'develop' into arrays-proofJames Pollard2020-06-093-25/+64
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| * Finished main proof with small assumptionsYann Herklotz2020-06-043-25/+63
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-031-0/+5
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| * Uncomment proofYann Herklotz2020-06-031-0/+5
* | HTLgenspec status in line with developJames Pollard2020-06-031-0/+1
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-031-2/+2
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| * Add proof to final_statesYann Herklotz2020-06-021-2/+2
* | Update HTL semantics to support arrays.James Pollard2020-06-022-19/+32
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-021-2/+33
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| * Add proof for equivalence of movYann Herklotz2020-06-021-2/+33
* | Paramterise associations type to avoid some duplication.James Pollard2020-06-021-44/+40
* | First draft of array semantics.James Pollard2020-06-011-112/+188
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-011-8/+15
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| * Copy over RTL global stateYann Herklotz2020-06-011-8/+15
* | Merge branch 'develop' into arrays-proofJames Pollard2020-05-305-177/+756
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| * Fix compilation moving to PTreeYann Herklotz2020-05-293-11/+14
| * Fix indentationYann Herklotz2020-05-291-6/+6
| * New and improved AssocmapYann Herklotz2020-05-291-7/+32
| * Change AssocMap to Maps.PTreeYann Herklotz2020-05-291-47/+66
| * Finish Assocmap proofsYann Herklotz2020-05-281-0/+59
| * Add more proofs and remove AdmittedYann Herklotz2020-05-272-16/+51
| * Add HTLgenYann Herklotz2020-05-241-5/+4
| * Finish the proof with most assumptionsYann Herklotz2020-05-211-6/+11
| * Fix the semantics to properly evaluate the stateYann Herklotz2020-05-201-2/+4
| * Switch position of empty ruleYann Herklotz2020-05-201-4/+4
| * Fix definitions in Value and add lemmasYann Herklotz2020-05-201-7/+35
| * Add theorems about mergeYann Herklotz2020-05-201-2/+12
| * Add lessdef for valuesYann Herklotz2020-05-081-3/+10
| * Add AssocMapYann Herklotz2020-05-084-47/+93
| * Redefine HTL for intermediate Verilog languageYann Herklotz2020-05-071-76/+69
| * Use associations instead of stateYann Herklotz2020-05-072-70/+69
| * Rename assoclist to assocsetYann Herklotz2020-05-072-28/+28
| * Add changes to valueYann Herklotz2020-05-061-2/+9
| * Refine test fileYann Herklotz2020-05-051-5/+2
| * Minimised manual simulationYann Herklotz2020-05-052-45/+14
| * Simplifications to proofYann Herklotz2020-05-053-18/+15
| * Finish manual simulationYann Herklotz2020-05-052-5/+68
| * Add equality check for valueYann Herklotz2020-05-042-16/+22
| * Refine the semanticsYann Herklotz2020-05-043-56/+130
| * Add code to debug execution of HLSYann Herklotz2020-05-031-0/+73
| * Add hex notation to valuesYann Herklotz2020-05-031-0/+9
| * Change to StateYann Herklotz2020-05-031-21/+22
| * Add CompCert semantics for VerilogYann Herklotz2020-04-241-81/+152
| * Add valueToInt functionYann Herklotz2020-04-241-0/+3
| * Add stmnt_runp inductiveYann Herklotz2020-04-221-27/+106
* | (Tentatively) working stack array/memory support.James Pollard2020-05-262-0/+12
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* Remove unnecessary LemmaYann Herklotz2020-04-221-8/+1
* Use State in semantics instead of splitting it upYann Herklotz2020-04-221-95/+98
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