aboutsummaryrefslogtreecommitdiffstats
path: root/src/verilog
Commit message (Expand)AuthorAgeFilesLines
* Add a call instruction to HTL. Use it for Icall.Michalis Pardalos2020-11-302-3/+30
* Revert changes relating to instance generationMichalis Pardalos2020-11-274-48/+16
* Add wires and use them for output of instancesMichalis Pardalos2020-11-203-10/+13
* Separate HTL instantiations from Verilog onesMichalis Pardalos2020-11-205-18/+20
* Print HTL args as reg_{n}, not x{n}Michalis Pardalos2020-11-201-7/+7
* Translate instantiations from HTL to verilogMichalis Pardalos2020-11-202-1/+3
* Print instantiations in HTL outputMichalis Pardalos2020-11-203-14/+29
* Add a field in HTL modules for instancesMichalis Pardalos2020-11-203-5/+5
* Print all modules in verilog outputMichalis Pardalos2020-11-201-13/+11
* Generate (invalid) module instantiations for callsMichalis Pardalos2020-11-202-6/+13
* Add html generation and clean Coq filesYann Herklotz2020-08-133-5/+2
* Finish istore and iload without any admitsYann Herklotz2020-08-041-1/+2
* Fix iload proofYann Herklotz2020-08-041-0/+4
* More renames to get it to compileYann Herklotz2020-07-242-4/+6
* Change name to VericertYann Herklotz2020-07-149-17/+17
* Fixes to operatorsYann Herklotz2020-07-071-3/+2
* Only translate_cond leftYann Herklotz2020-07-071-1/+3
* No admitted in Deterministic proofYann Herklotz2020-07-072-12/+8
* Add top level backward simulationYann Herklotz2020-07-061-8/+2
* HTLgenproof compiles againYann Herklotz2020-07-062-7/+11
* No addmitted in VeriloggenproofYann Herklotz2020-07-051-8/+12
* Remove admitted in mis_stepp_VdeclYann Herklotz2020-07-051-4/+3
* Finish most of VeriloggenproofYann Herklotz2020-07-053-7/+9
* Working on determinacy proof.James Pollard2020-07-041-2/+133
* Fixing HTLgenproofYann Herklotz2020-07-033-13/+20
* Add new value type to fix Iop proofYann Herklotz2020-07-034-65/+215
* Addition to int_add_v2Yann Herklotz2020-07-031-3/+13
* Updates to Iop proofYann Herklotz2020-07-031-1/+78
* Switch to uvalueToZ in lessdef.James Pollard2020-07-021-2/+2
* Complete ZToValue_valueToNat.James Pollard2020-07-021-9/+18
* Push current stateYann Herklotz2020-07-021-0/+2
* Merge remote-tracking branch 'james/develop' into developYann Herklotz2020-07-011-28/+41
|\
| * Improve (?) automation.James Pollard2020-07-011-28/+41
* | Add HTL pretty printerYann Herklotz2020-06-301-0/+81
* | Add htl pretty printingYann Herklotz2020-06-302-1/+3
|/
* Add command line flags for initial blockYann Herklotz2020-06-301-0/+10
* Make the proofs more conciseYann Herklotz2020-06-301-17/+21
* Add equivalence between int add value addYann Herklotz2020-06-301-10/+54
* Work on addition proofYann Herklotz2020-06-291-1/+21
* Fix proof again with Verilog semantics changesYann Herklotz2020-06-281-0/+12
* Merge remote-tracking branch 'james/arrays-proof' into developYann Herklotz2020-06-281-0/+53
|\
| * Work on proof.James Pollard2020-06-281-0/+53
* | Fix Verilog semantics and fix order of always blocksYann Herklotz2020-06-261-1/+1
* | Progress on proof of VeriloggenYann Herklotz2020-06-252-1/+5
* | Work on Veriloggen proofYann Herklotz2020-06-251-3/+4
|/
* Fixes to make develop compileYann Herklotz2020-06-241-5/+3
* More to proofYann Herklotz2020-06-231-7/+9
* Admit the value proofYann Herklotz2020-06-221-3/+5
* Merge branch 'arrays-proof' into developYann Herklotz2020-06-221-0/+5
|\
| * Finish structure of Aindexed2scaled ILoad proof.James Pollard2020-06-201-0/+5