Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | Add simulation diagram | Yann Herklotz | 2020-05-08 | 1 | -5/+53 | |
| * | Add lessdef for values | Yann Herklotz | 2020-05-08 | 1 | -3/+10 | |
| * | Add AssocMap | Yann Herklotz | 2020-05-08 | 4 | -47/+93 | |
| * | Add match_states Inductive | Yann Herklotz | 2020-05-07 | 1 | -0/+29 | |
| * | Remove HTLgen and create the specification | Yann Herklotz | 2020-05-07 | 2 | -163/+92 | |
| * | Redefine HTL for intermediate Verilog language | Yann Herklotz | 2020-05-07 | 2 | -76/+87 | |
| * | Use associations instead of state | Yann Herklotz | 2020-05-07 | 2 | -70/+69 | |
| * | Rename assoclist to assocset | Yann Herklotz | 2020-05-07 | 2 | -28/+28 | |
| * | Remove Admitted Maps Lemma | Yann Herklotz | 2020-05-07 | 1 | -6/+0 | |
| * | Add changes to value | Yann Herklotz | 2020-05-06 | 1 | -2/+9 | |
| * | Refine test file | Yann Herklotz | 2020-05-05 | 1 | -5/+2 | |
| * | Minimised manual simulation | Yann Herklotz | 2020-05-05 | 2 | -45/+14 | |
| * | Simplifications to proof | Yann Herklotz | 2020-05-05 | 3 | -18/+15 | |
| * | Finish manual simulation | Yann Herklotz | 2020-05-05 | 2 | -5/+68 | |
| * | Add equality check for value | Yann Herklotz | 2020-05-04 | 7 | -21/+27 | |
| * | Refine the semantics | Yann Herklotz | 2020-05-04 | 3 | -56/+130 | |
| * | Add code to debug execution of HLS | Yann Herklotz | 2020-05-03 | 1 | -0/+73 | |
| * | Add proofs and specification of Verilog conversion | Yann Herklotz | 2020-05-03 | 2 | -0/+158 | |
| * | Add state transition conversion functions | Yann Herklotz | 2020-05-03 | 1 | -2/+14 | |
| * | Add hex notation to values | Yann Herklotz | 2020-05-03 | 1 | -0/+9 | |
| * | Change to State | Yann Herklotz | 2020-05-03 | 1 | -21/+22 | |
| * | Add documentation and conform to specification | Yann Herklotz | 2020-04-29 | 1 | -24/+41 | |
| * | Add CompCert semantics for Verilog | Yann Herklotz | 2020-04-24 | 1 | -81/+152 | |
| * | Add valueToInt function | Yann Herklotz | 2020-04-24 | 1 | -0/+3 | |
| * | Add stmnt_runp inductive | Yann Herklotz | 2020-04-22 | 1 | -27/+106 | |
* | | Stop using tuples for register declarations | James Pollard | 2020-05-30 | 1 | -37/+39 | |
* | | Fix addressing to add support for arbitraty pointer operations | James Pollard | 2020-05-27 | 1 | -10/+19 | |
* | | Bug fix: stack address normalisation | James Pollard | 2020-05-26 | 1 | -1/+1 | |
* | | (Tentatively) working stack array/memory support. | James Pollard | 2020-05-26 | 3 | -37/+62 | |
* | | Add pattern matches and plumb through stack reg | James Pollard | 2020-05-25 | 1 | -5/+21 | |
* | | Start work on array support | James Pollard | 2020-05-25 | 1 | -0/+1 | |
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* | Return the actual result of the module | Yann Herklotz | 2020-04-22 | 1 | -2/+5 | |
* | Remove unnecessary Lemma | Yann Herklotz | 2020-04-22 | 1 | -8/+1 | |
* | Use State in semantics instead of splitting it up | Yann Herklotz | 2020-04-22 | 1 | -95/+98 | |
* | Improve printing of results | Yann Herklotz | 2020-04-22 | 2 | -7/+13 | |
* | Fix Verilog.v | Yann Herklotz | 2020-04-17 | 1 | -1/+1 | |
* | Add main module run | Yann Herklotz | 2020-04-17 | 2 | -51/+79 | |
* | Fix printing with new Verilog AST | Yann Herklotz | 2020-04-17 | 2 | -26/+54 | |
* | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 | |
* | Extract simulator | Yann Herklotz | 2020-04-17 | 2 | -5/+5 | |
* | Add Simulator.v | Yann Herklotz | 2020-04-17 | 1 | -0/+32 | |
* | Add do notation for option | Yann Herklotz | 2020-04-15 | 1 | -0/+11 | |
* | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 | |
* | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 | |
* | Create Value module for bitvectors | Yann Herklotz | 2020-04-15 | 1 | -0/+217 | |
* | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 | |
* | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 | |
* | Fix extraction on linux | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
* | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 3 | -112/+181 | |
* | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 |