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* Fix pretty printing bug in VerilogYann Herklotz2020-11-021-2/+2
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* WIP on RTLBlock semanticsYann Herklotz2020-11-021-12/+98
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* Add optimisations to outputYann Herklotz2020-11-022-15/+74
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* Add flag to control if scheduling is activeYann Herklotz2020-11-011-0/+1
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* Improve performance dramatically for RTLBlock generationYann Herklotz2020-10-311-17/+19
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* Fix bugs in SchedulingYann Herklotz2020-10-311-3/+12
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* Add tbl_to_casestatement into extractionYann Herklotz2020-10-262-11/+26
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* Fix build error with ValueValYann Herklotz2020-10-261-2/+8
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* Add printing of intermediate rtlblock languageYann Herklotz2020-10-233-1/+7
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* Fix printing of negative numbersYann Herklotz2020-10-231-1/+5
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* Fix scheduling for loads and stores with WAR dependenciesYann Herklotz2020-10-231-16/+120
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* Finish implementing scheduling and add top level exportYann Herklotz2020-10-203-5/+11
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* Fix bug in schedulingYann Herklotz2020-10-201-1/+1
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* Add top level functions to scheduleYann Herklotz2020-10-191-49/+115
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* Revert ValueInt.vYann Herklotz2020-10-181-79/+23
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* Add output to schedulingYann Herklotz2020-10-181-25/+282
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* Add renumbering to compiler passesYann Herklotz2020-10-181-0/+1
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* More changes to HTLBlockgenYann Herklotz2020-10-151-2/+2
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* Add HTLBlockgen and more schedulingYann Herklotz2020-10-153-42/+921
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* Add long and bool support to valueYann Herklotz2020-10-061-23/+79
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* Add fixes to run scheduling on compilationYann Herklotz2020-09-032-1/+15
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* Scheduling added to partitioningYann Herklotz2020-09-031-3/+2
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* Add schedulingYann Herklotz2020-09-032-0/+181
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* Fix bug for basic block construction in loopsYann Herklotz2020-08-311-3/+7
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* Add working partitioning algorithmYann Herklotz2020-08-314-42/+175
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* Continue on Partitioning algorithmYann Herklotz2020-08-303-14/+66
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* Add RTLBlock intermediate languageYann Herklotz2020-08-3019-3/+178
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* Add html generation and clean Coq filesYann Herklotz2020-08-134-7/+3
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* Finished all the proofsv1.0.0Yann Herklotz2020-08-133-39/+46
| | | | Removed support for case statements temporarily.
* Remove unnecessary commented proofYann Herklotz2020-08-121-23/+0
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* Finish proof of conditionalsYann Herklotz2020-08-121-4/+11
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* Nearly finished all proofsYann Herklotz2020-08-121-48/+228
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* Remove alignment constraint during translation.James Pollard2020-08-112-67/+69
| | | | This is now inferred from the memory model.
* Remove last admits from istoreYann Herklotz2020-08-041-2/+3
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* Finish istore and iload without any admitsYann Herklotz2020-08-042-119/+115
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* No admitted in iload proofYann Herklotz2020-08-041-38/+72
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* Merge remote-tracking branch 'james/develop' into developYann Herklotz2020-08-041-5/+6
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| * Fix broken proof.James Pollard2020-08-041-5/+6
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* | Add expr_ok proofYann Herklotz2020-08-041-11/+25
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* Fix first part of istoreYann Herklotz2020-08-041-40/+43
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* Fix iload proofYann Herklotz2020-08-042-43/+52
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* Add proof of divisibilityYann Herklotz2020-08-041-21/+14
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* Remove check mpassYann Herklotz2020-07-241-2/+0
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* More renames to get it to compileYann Herklotz2020-07-244-6/+9
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* Rename to VericertlibYann Herklotz2020-07-171-0/+0
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* Change name to VericertYann Herklotz2020-07-1423-53/+52
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* Fixes to operatorsYann Herklotz2020-07-074-6/+12
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* Finished transl_condYann Herklotz2020-07-072-62/+45
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* Only translate_cond leftYann Herklotz2020-07-074-17/+252
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* No admitted in Deterministic proofYann Herklotz2020-07-073-14/+10
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