Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge branch 'master' into michalis-merge | Yann Herklotz | 2021-02-16 | 3 | -1/+621 |
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| * | Remove dependency on Tactics | Yann Herklotz | 2021-02-16 | 1 | -1/+0 |
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| * | Add functional units and Sat | Yann Herklotz | 2021-02-16 | 2 | -0/+621 |
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* | | Make top-level theorems pass | Yann Herklotz | 2021-02-16 | 3 | -48/+53 |
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* | | Add changes to HTL as they weren't merged | Yann Herklotz | 2021-02-16 | 1 | -53/+122 |
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* | | Merge branch 'michalis' of https://github.com/mpardalos/vericert into ↵ | Yann Herklotz | 2021-02-16 | 14 | -183/+769 |
|\ \ | |/ |/| | | | michalis-merge | ||||
| * | Implement join. Completes implementation | Michalis Pardalos | 2021-02-15 | 1 | -4/+8 |
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| * | Group all verilog translation code | Michalis Pardalos | 2021-02-15 | 1 | -43/+44 |
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| * | Make HTLFork translation use renumbered registers | Michalis Pardalos | 2021-02-15 | 1 | -63/+69 |
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| * | Add PTree traversal functions for vericert monads | Michalis Pardalos | 2021-02-15 | 1 | -1/+20 |
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| * | Add an indexed filter function to PTree | Michalis Pardalos | 2021-02-12 | 1 | -0/+27 |
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| * | Implemented fork and wait (incorrectly) | Michalis Pardalos | 2021-02-12 | 1 | -46/+70 |
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| * | Reformat | Michalis Pardalos | 2021-02-09 | 1 | -5/+5 |
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| * | Add wait instruction to HTL control path | Michalis Pardalos | 2021-01-26 | 7 | -76/+152 |
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| * | Separate HTL call into fork and join | Michalis Pardalos | 2021-01-26 | 5 | -20/+62 |
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| * | Inlined modules are valid verilog, use correct clk | Michalis Pardalos | 2021-01-26 | 3 | -16/+50 |
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| * | Renumbering removes name conflicts | Michalis Pardalos | 2021-01-25 | 1 | -197/+226 |
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| * | Implement renumbering (wrong) | Michalis Pardalos | 2021-01-25 | 4 | -51/+269 |
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| * | Get everything compiling | Michalis Pardalos | 2021-01-18 | 2 | -2/+5 |
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| * | Get top-level proofs passing. | Michalis Pardalos | 2020-12-01 | 1 | -28/+26 |
| | | | | | | | | Needed change because inlining was removed. | ||||
| * | Get proofs in HTLgenproof to pass | Michalis Pardalos | 2020-12-01 | 1 | -11/+6 |
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| * | Update proofs in HTLgenspec | Michalis Pardalos | 2020-12-01 | 1 | -4/+17 |
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| * | Declare dst reg for call instr | Michalis Pardalos | 2020-12-01 | 1 | -0/+1 |
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| * | Add a call instruction to HTL. Use it for Icall. | Michalis Pardalos | 2020-11-30 | 8 | -97/+190 |
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| * | Revert changes relating to instance generation | Michalis Pardalos | 2020-11-27 | 8 | -205/+60 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Add todo for missing logic around instantiations" This reverts commit 303a45374643f75698c61f062899973d2c297831. Revert "Add wires and use them for output of instances" This reverts commit a72f26319dabca414a2b576424b9f72afaca161c. Revert "Separate HTL instantiations from Verilog ones" This reverts commit 653c8729f4322f538aa7116c5e311c884b3c5047. Revert "Translate instantiations from HTL to verilog" This reverts commit 982e6c69a52e8ec4e677147004cc5472f8a80d6d. Revert "Print instantiations in HTL output" This reverts commit 9b87637d3e4d6a75dee1221b017e3ccf6632642e. Revert "Add a field in HTL modules for instances" This reverts commit d79dae026b150e9671e0aa7262f6aa2d1d302502. Revert "Generate (invalid) module instantiations for calls" This reverts commit dfaa3a9cbc07649feea3220693a8a854a32eafb6. | ||||
| * | Add todo for missing logic around instantiations | Michalis Pardalos | 2020-11-20 | 1 | -0/+1 |
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| * | Add wires and use them for output of instances | Michalis Pardalos | 2020-11-20 | 5 | -23/+55 |
| | | | | | | | | | | | | | | | | [WIP] Add wires to HTL [WIP] Add wires to verilog [WIP] Use wire for finished signal [WIP] merge wire and scl [WIP] Fix wrong reg in ICall translation | ||||
| * | Separate HTL instantiations from Verilog ones | Michalis Pardalos | 2020-11-20 | 7 | -21/+30 |
| | | | | | | | | | | | | | | | | | | | | | | In HTL, they reference their data arguments, destination, and finished control signal. Meanwhile, in Verilog, they just contain an unstructured list of parameters. This is done because when modules are generated in the HTL stage we do not have access to any of the instantiating module's control signals (they are declared after the entirety of the module has been translated). Also, I believe, these signals are not part of the HTL semantics. | ||||
| * | Print HTL args as reg_{n}, not x{n} | Michalis Pardalos | 2020-11-20 | 1 | -7/+7 |
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| * | Translate instantiations from HTL to verilog | Michalis Pardalos | 2020-11-20 | 3 | -2/+7 |
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| * | Print instantiations in HTL output | Michalis Pardalos | 2020-11-20 | 3 | -14/+29 |
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| * | Add a field in HTL modules for instances | Michalis Pardalos | 2020-11-20 | 5 | -37/+102 |
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| * | Print all modules in verilog output | Michalis Pardalos | 2020-11-20 | 1 | -13/+11 |
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| * | Generate (invalid) module instantiations for calls | Michalis Pardalos | 2020-11-20 | 5 | -14/+29 |
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* | | Add more legible names to variables | Yann Herklotz | 2021-02-12 | 1 | -1/+17 |
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* | | Add temporary fixes to get everything to compile | Yann Herklotz | 2021-02-12 | 7 | -36/+386 |
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* | | Fix state generation for if-conversion | Yann Herklotz | 2021-02-03 | 4 | -14/+21 |
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* | | Fix scheduling for if-conversion | Yann Herklotz | 2021-02-03 | 1 | -14/+90 |
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* | | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 7 | -41/+92 |
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* | | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -3/+65 |
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* | | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -0/+32 |
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* | | Add Vrange and predicates | Yann Herklotz | 2021-02-02 | 8 | -66/+95 |
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* | | Fix OCaml files for compilation | Yann Herklotz | 2021-01-31 | 4 | -92/+94 |
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* | | Fix compilation of Coq | Yann Herklotz | 2021-01-30 | 2 | -19/+48 |
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* | | Fix proofs with better defined equality | Yann Herklotz | 2021-01-30 | 2 | -31/+57 |
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* | | Fix definitions of proofs some more | Yann Herklotz | 2021-01-29 | 4 | -106/+162 |
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* | | Fix the proof for RTLPargen | Yann Herklotz | 2021-01-29 | 1 | -32/+33 |
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* | | Fix HTLPargen and RTLPargen | Yann Herklotz | 2021-01-29 | 2 | -56/+178 |
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* | | Refactoring RTLBlock and RTLPar | Yann Herklotz | 2021-01-29 | 3 | -297/+205 |
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* | | Finish all proofs except executing basic blocks | Yann Herklotz | 2021-01-27 | 1 | -1/+4 |
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