| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Finish a merging proof | Yann Herklotz | 2021-03-21 | 1 | -12/+30 | |
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| | * | Add many lemmas about arrays | Yann Herklotz | 2021-03-21 | 2 | -29/+250 | |
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| | * | Add check for ram in module | Yann Herklotz | 2021-03-20 | 1 | -16/+161 | |
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| | * | Prove very top-level theorem | Yann Herklotz | 2021-03-19 | 2 | -83/+176 | |
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| | * | Fix proof with new array matching | Yann Herklotz | 2021-03-17 | 1 | -20/+47 | |
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| | * | Fix main proofs with smaller admits | Yann Herklotz | 2021-03-17 | 1 | -25/+50 | |
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| | * | Proof of equivalent stmnt runs with matching start | Yann Herklotz | 2021-03-17 | 1 | -155/+263 | |
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| | * | Prove one case of transf_code correct | Yann Herklotz | 2021-03-16 | 1 | -1/+54 | |
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| | * | Greatly simplify proof | Yann Herklotz | 2021-03-16 | 1 | -44/+23 | |
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| | * | Finish proof of simple transformation | Yann Herklotz | 2021-03-16 | 1 | -0/+90 | |
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| | * | Fix memory inferrence generation | Yann Herklotz | 2021-03-15 | 1 | -28/+32 | |
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| | * | Move implicit args | Yann Herklotz | 2021-03-15 | 1 | -2/+2 | |
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| | * | Fix Verilog imports | Yann Herklotz | 2021-03-14 | 1 | -14/+20 | |
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| | * | Remove comments in Verilog.v | Yann Herklotz | 2021-03-14 | 1 | -194/+0 | |
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| | * | Prove top-level theorem with admitted theorems | Yann Herklotz | 2021-03-12 | 2 | -159/+193 | |
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| | * | Try and fix identity proof in Memorygen | Yann Herklotz | 2021-03-12 | 1 | -1/+12 | |
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| | * | Prove idempotency of array merge | Yann Herklotz | 2021-03-11 | 2 | -20/+86 | |
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| | * | Update RAM generation proofs | Yann Herklotz | 2021-03-09 | 3 | -70/+472 | |
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| | * | Add negative edge reasoning to HTLgenproof | Yann Herklotz | 2021-03-09 | 2 | -12/+109 | |
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| | * | Add RAM semantics to HTL and fix proof | Yann Herklotz | 2021-03-03 | 4 | -18/+132 | |
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| | * | Add implementation | Yann Herklotz | 2021-03-02 | 2 | -29/+80 | |
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| | * | Add option to turn on/off ram inferrence | Yann Herklotz | 2021-03-02 | 4 | -2/+9 | |
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| | * | Add RAM to HTL | Yann Herklotz | 2021-03-02 | 4 | -1/+4 | |
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| | * | Fix memory generation by generating a power of 2 | Yann Herklotz | 2021-03-02 | 1 | -34/+50 | |
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| | * | Print Verilog in reverse order | Yann Herklotz | 2021-03-02 | 1 | -1/+1 | |
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| | * | Add Verilog generation for rams | Yann Herklotz | 2021-03-02 | 1 | -18/+47 | |
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| | * | Admit Veriloggenproof | Yann Herklotz | 2021-03-02 | 1 | -2/+3 | |
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| | * | Finish initial implementation of memory gen | Yann Herklotz | 2021-03-01 | 2 | -2/+89 | |
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| | * | Change lists in case statements to stmnt_list | Yann Herklotz | 2021-03-01 | 6 | -12/+30 | |
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| | * | Add initial memory generation | Yann Herklotz | 2021-03-01 | 1 | -0/+17 | |
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| * | | Use new HTLgenspec in proof | Michalis Pardalos | 2021-08-22 | 1 | -3/+27 | |
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| * | | Move list lemmas to own file | Michalis Pardalos | 2021-08-22 | 2 | -21/+28 | |
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| * | | Add length args = length params to Icall spec | Michalis Pardalos | 2021-08-21 | 1 | -44/+80 | |
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| * | | Strengthen HTLgenspec | Michalis Pardalos | 2021-08-20 | 1 | -9/+14 | |
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| * | | More progress in Icall proof | Michalis Pardalos | 2021-08-19 | 1 | -14/+16 | |
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| * | | Find called module in Icall proof | Michalis Pardalos | 2021-08-19 | 4 | -29/+39 | |
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| * | | Complete HTLspec (mostly) | Michalis Pardalos | 2021-08-12 | 3 | -52/+133 | |
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| * | | Tie clocks in the ApplyExternctrl pass | Michalis Pardalos | 2021-08-12 | 2 | -2/+7 | |
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| * | | Get HTLgenproof passing with updated spec | Michalis Pardalos | 2021-08-06 | 1 | -3/+3 | |
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| * | | Correct lookup for called funcs, simplify tr_module | Michalis Pardalos | 2021-08-04 | 3 | -32/+61 | |
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| * | | Check whether callee is internal for Icall | Michalis Pardalos | 2021-08-02 | 2 | -25/+24 | |
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| * | | Add "join state is <=Int.max_unsigned" to HTLgenspec | Michalis Pardalos | 2021-06-10 | 2 | -10/+13 | |
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| * | | Remove all Admitted from top-level Compiler.v | Michalis Pardalos | 2021-06-10 | 7 | -425/+618 | |
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| * | | Get top-level (Compiler) proof closer to Qed | Michalis Pardalos | 2021-06-08 | 1 | -3/+27 | |
| | | | | | | | | | Add Renaming and ApplyExternctrl to correctness statement | |||||
| * | | Make externctrl application its own HTL pass | Michalis Pardalos | 2021-06-06 | 4 | -185/+229 | |
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| * | | Move HTL renaming pass to own file | Michalis Pardalos | 2021-06-06 | 5 | -242/+249 | |
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| * | | Add explanations for axioms | Michalis Pardalos | 2021-05-18 | 1 | -11/+13 | |
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| * | | Add axiom that only the main contains stores | Michalis Pardalos | 2021-05-18 | 1 | -4/+10 | |
| | | | | | | | | | | | This is true due to the inlining pass. It should be checked in the translation and be added in the translation spec. | |||||
| * | | Qed on top-level correctness lemma | Michalis Pardalos | 2021-05-18 | 1 | -2/+2 | |
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| * | | Update lemmata broken by changes to semantics | Michalis Pardalos | 2021-05-18 | 1 | -42/+35 | |
| | | | | | | | | | | | | | * Removed calls to match_externctrl_tac. Carried forward without need for the tactic * Admitted match_frames goals. They should be easy enough to fix | |||||
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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