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author | Yann Herklotz <git@yannherklotz.com> | 2019-10-18 14:29:07 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-18 14:29:07 +0100 |
commit | e7f57642f068650ea362201b239efad1c9a841d9 (patch) | |
tree | 2d68c28c0644089b9afcfc21fc05f88d50ef6703 | |
parent | 349c1fa290c068a0f4100469e7485d062dd995ce (diff) | |
download | verismith-e7f57642f068650ea362201b239efad1c9a841d9.tar.gz verismith-e7f57642f068650ea362201b239efad1c9a841d9.zip |
Rename Sim to Tool
-rw-r--r-- | src/Verismith.hs | 6 | ||||
-rw-r--r-- | src/Verismith/Config.hs | 8 | ||||
-rw-r--r-- | src/Verismith/Fuzz.hs | 37 | ||||
-rw-r--r-- | src/Verismith/Reduce.hs | 4 | ||||
-rw-r--r-- | src/Verismith/Report.hs | 4 | ||||
-rw-r--r-- | src/Verismith/Tool.hs (renamed from src/Verismith/Sim.hs) | 18 | ||||
-rw-r--r-- | src/Verismith/Tool/Icarus.hs (renamed from src/Verismith/Sim/Icarus.hs) | 8 | ||||
-rw-r--r-- | src/Verismith/Tool/Identity.hs (renamed from src/Verismith/Sim/Identity.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Tool/Internal.hs (renamed from src/Verismith/Sim/Internal.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Tool/Quartus.hs (renamed from src/Verismith/Sim/Quartus.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Tool/Template.hs (renamed from src/Verismith/Sim/Template.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Tool/Vivado.hs (renamed from src/Verismith/Sim/Vivado.hs) | 8 | ||||
-rw-r--r-- | src/Verismith/Tool/XST.hs (renamed from src/Verismith/Sim/XST.hs) | 8 | ||||
-rw-r--r-- | src/Verismith/Tool/Yosys.hs (renamed from src/Verismith/Sim/Yosys.hs) | 8 | ||||
-rw-r--r-- | verismith.cabal | 18 |
15 files changed, 72 insertions, 77 deletions
diff --git a/src/Verismith.hs b/src/Verismith.hs index e7d3ce6..85deca3 100644 --- a/src/Verismith.hs +++ b/src/Verismith.hs @@ -30,7 +30,7 @@ module Verismith , module Verismith.Verilog , module Verismith.Config , module Verismith.Circuit - , module Verismith.Sim + , module Verismith.Tool , module Verismith.Fuzz , module Verismith.Report ) @@ -65,8 +65,8 @@ import Verismith.Generate import Verismith.Reduce import Verismith.Report import Verismith.Result -import Verismith.Sim -import Verismith.Sim.Internal +import Verismith.Tool +import Verismith.Tool.Internal import Verismith.Verilog import Verismith.Verilog.Parser (parseSourceInfoFile) diff --git a/src/Verismith/Config.hs b/src/Verismith/Config.hs index 9d37fd2..decf1fb 100644 --- a/src/Verismith/Config.hs +++ b/src/Verismith/Config.hs @@ -92,10 +92,10 @@ import Paths_verismith (version) import Shelly (toTextIgnore) import Toml (TomlCodec, (.=)) import qualified Toml -import Verismith.Sim.Quartus -import Verismith.Sim.Vivado -import Verismith.Sim.XST -import Verismith.Sim.Yosys +import Verismith.Tool.Quartus +import Verismith.Tool.Vivado +import Verismith.Tool.XST +import Verismith.Tool.Yosys -- $conf -- diff --git a/src/Verismith/Fuzz.hs b/src/Verismith/Fuzz.hs index 1f86739..81c00a0 100644 --- a/src/Verismith/Fuzz.hs +++ b/src/Verismith/Fuzz.hs @@ -59,9 +59,9 @@ import Verismith.Internal import Verismith.Reduce import Verismith.Report import Verismith.Result -import Verismith.Sim.Icarus -import Verismith.Sim.Internal -import Verismith.Sim.Yosys +import Verismith.Tool.Icarus +import Verismith.Tool.Internal +import Verismith.Tool.Yosys import Verismith.Verilog.AST import Verismith.Verilog.CodeGen @@ -194,24 +194,19 @@ equivalence src = do equiv a b = toolRun ("equivalence check for " <> toText a <> " and " <> toText b) . runResultT - $ do - make dir - pop dir $ do - liftSh $ do - cp - ( fromText ".." - </> fromText (toText a) - </> synthOutput a - ) - $ synthOutput a - cp - ( fromText ".." - </> fromText (toText b) - </> synthOutput b - ) - $ synthOutput b - writefile "rtl.v" $ genSource src - runEquiv a b src + $ do make dir + pop dir $ do + liftSh $ do + cp ( fromText ".." + </> fromText (toText a) + </> synthOutput a + ) $ synthOutput a + cp ( fromText ".." + </> fromText (toText b) + </> synthOutput b + ) $ synthOutput b + writefile "rtl.v" $ genSource src + runEquiv a b src where dir = fromText $ "equiv_" <> toText a <> "_" <> toText b simulation :: (MonadIO m, MonadSh m) => SourceInfo -> Fuzz m () diff --git a/src/Verismith/Reduce.hs b/src/Verismith/Reduce.hs index 69674cc..88f0b42 100644 --- a/src/Verismith/Reduce.hs +++ b/src/Verismith/Reduce.hs @@ -49,8 +49,8 @@ import qualified Shelly import Shelly.Lifted (MonadSh, liftSh) import Verismith.Internal import Verismith.Result -import Verismith.Sim -import Verismith.Sim.Internal +import Verismith.Tool +import Verismith.Tool.Internal import Verismith.Verilog import Verismith.Verilog.AST import Verismith.Verilog.Mutate diff --git a/src/Verismith/Report.hs b/src/Verismith/Report.hs index b074be4..6c25f5c 100644 --- a/src/Verismith/Report.hs +++ b/src/Verismith/Report.hs @@ -63,8 +63,8 @@ import qualified Text.Blaze.Html5.Attributes as A import Verismith.Config import Verismith.Internal import Verismith.Result -import Verismith.Sim -import Verismith.Sim.Internal +import Verismith.Tool +import Verismith.Tool.Internal -- | Common type alias for synthesis results type UResult = Result Failed () diff --git a/src/Verismith/Sim.hs b/src/Verismith/Tool.hs index 5e31985..7e41180 100644 --- a/src/Verismith/Sim.hs +++ b/src/Verismith/Tool.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim +Module : Verismith.Tool Description : Simulator implementations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Simulator implementations. -} -module Verismith.Sim +module Verismith.Tool ( -- * Simulators -- ** Icarus @@ -42,10 +42,10 @@ module Verismith.Sim ) where -import Verismith.Sim.Icarus -import Verismith.Sim.Identity -import Verismith.Sim.Internal -import Verismith.Sim.Quartus -import Verismith.Sim.Vivado -import Verismith.Sim.XST -import Verismith.Sim.Yosys +import Verismith.Tool.Icarus +import Verismith.Tool.Identity +import Verismith.Tool.Internal +import Verismith.Tool.Quartus +import Verismith.Tool.Vivado +import Verismith.Tool.XST +import Verismith.Tool.Yosys diff --git a/src/Verismith/Sim/Icarus.hs b/src/Verismith/Tool/Icarus.hs index 003f1de..b783033 100644 --- a/src/Verismith/Sim/Icarus.hs +++ b/src/Verismith/Tool/Icarus.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Icarus +Module : Verismith.Tool.Icarus Description : Icarus verilog module. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Icarus verilog module. -} -module Verismith.Sim.Icarus +module Verismith.Tool.Icarus ( Icarus(..) , defaultIcarus , runSimIc @@ -39,8 +39,8 @@ import Numeric (readInt) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import Verismith.Sim.Internal -import Verismith.Sim.Template +import Verismith.Tool.Internal +import Verismith.Tool.Template import Verismith.Verilog.AST import Verismith.Verilog.BitVec import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/Identity.hs b/src/Verismith/Tool/Identity.hs index 89c6b36..93b05d5 100644 --- a/src/Verismith/Sim/Identity.hs +++ b/src/Verismith/Tool/Identity.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Identity +Module : Verismith.Tool.Identity Description : The identity simulator and synthesiser. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX The identity simulator and synthesiser. -} -module Verismith.Sim.Identity +module Verismith.Tool.Identity ( Identity(..) , defaultIdentity ) @@ -21,7 +21,7 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly (FilePath) import Shelly.Lifted (writefile) -import Verismith.Sim.Internal +import Verismith.Tool.Internal import Verismith.Verilog.AST import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/Internal.hs b/src/Verismith/Tool/Internal.hs index bcbc3af..c2e3a0c 100644 --- a/src/Verismith/Sim/Internal.hs +++ b/src/Verismith/Tool/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Internal +Module : Verismith.Tool.Internal Description : Class of the simulator. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool. {-# LANGUAGE DeriveFunctor #-} -module Verismith.Sim.Internal +module Verismith.Tool.Internal ( ResultSh , resultSh , Tool(..) diff --git a/src/Verismith/Sim/Quartus.hs b/src/Verismith/Tool/Quartus.hs index 5fb1e49..109d46c 100644 --- a/src/Verismith/Sim/Quartus.hs +++ b/src/Verismith/Tool/Quartus.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Quartus +Module : Verismith.Tool.Quartus Description : Quartus synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Quartus synthesiser implementation. -} -module Verismith.Sim.Quartus +module Verismith.Tool.Quartus ( Quartus(..) , defaultQuartus ) @@ -21,7 +21,7 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import Verismith.Sim.Internal +import Verismith.Tool.Internal import Verismith.Verilog.AST import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/Template.hs b/src/Verismith/Tool/Template.hs index 071e040..c0cbfe1 100644 --- a/src/Verismith/Sim/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Template +Module : Verismith.Tool.Template Description : Template file for different configuration files Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ Template file for different configuration files. {-# LANGUAGE QuasiQuotes #-} -module Verismith.Sim.Template +module Verismith.Tool.Template ( yosysSatConfig , yosysSimConfig , xstSynthConfig @@ -28,7 +28,7 @@ import qualified Data.Text as T import Prelude hiding (FilePath) import Shelly import Text.Shakespeare.Text (st) -import Verismith.Sim.Internal +import Verismith.Tool.Internal import Verismith.Verilog.AST import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/Vivado.hs b/src/Verismith/Tool/Vivado.hs index 2dad87d..272311e 100644 --- a/src/Verismith/Sim/Vivado.hs +++ b/src/Verismith/Tool/Vivado.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Vivado +Module : Verismith.Tool.Vivado Description : Vivado Synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Vivado Synthesiser implementation. -} -module Verismith.Sim.Vivado +module Verismith.Tool.Vivado ( Vivado(..) , defaultVivado ) @@ -21,8 +21,8 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import Verismith.Sim.Internal -import Verismith.Sim.Template +import Verismith.Tool.Internal +import Verismith.Tool.Template import Verismith.Verilog.AST import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/XST.hs b/src/Verismith/Tool/XST.hs index 9144ba7..c713e0b 100644 --- a/src/Verismith/Sim/XST.hs +++ b/src/Verismith/Tool/XST.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.XST +Module : Verismith.Tool.XST Description : XST (ise) simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ XST (ise) simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module Verismith.Sim.XST +module Verismith.Tool.XST ( XST(..) , defaultXST ) @@ -24,8 +24,8 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) import Text.Shakespeare.Text (st) -import Verismith.Sim.Internal -import Verismith.Sim.Template +import Verismith.Tool.Internal +import Verismith.Tool.Template import Verismith.Verilog.AST import Verismith.Verilog.CodeGen diff --git a/src/Verismith/Sim/Yosys.hs b/src/Verismith/Tool/Yosys.hs index 9805140..9c0a864 100644 --- a/src/Verismith/Sim/Yosys.hs +++ b/src/Verismith/Tool/Yosys.hs @@ -1,5 +1,5 @@ {-| -Module : Verismith.Sim.Yosys +Module : Verismith.Tool.Yosys Description : Yosys simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Yosys simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module Verismith.Sim.Yosys +module Verismith.Tool.Yosys ( Yosys(..) , defaultYosys , runEquiv @@ -29,8 +29,8 @@ import Shelly import Shelly.Lifted (liftSh) import Text.Shakespeare.Text (st) import Verismith.Result -import Verismith.Sim.Internal -import Verismith.Sim.Template +import Verismith.Tool.Internal +import Verismith.Tool.Template import Verismith.Verilog.AST import Verismith.Verilog.CodeGen import Verismith.Verilog.Mutate diff --git a/verismith.cabal b/verismith.cabal index 36a7777..7afb640 100644 --- a/verismith.cabal +++ b/verismith.cabal @@ -53,15 +53,15 @@ library , Verismith.Reduce , Verismith.Report , Verismith.Result - , Verismith.Sim - , Verismith.Sim.Icarus - , Verismith.Sim.Identity - , Verismith.Sim.Internal - , Verismith.Sim.Quartus - , Verismith.Sim.Template - , Verismith.Sim.Vivado - , Verismith.Sim.XST - , Verismith.Sim.Yosys + , Verismith.Tool + , Verismith.Tool.Icarus + , Verismith.Tool.Identity + , Verismith.Tool.Internal + , Verismith.Tool.Quartus + , Verismith.Tool.Template + , Verismith.Tool.Vivado + , Verismith.Tool.XST + , Verismith.Tool.Yosys , Verismith.Verilog , Verismith.Verilog.AST , Verismith.Verilog.BitVec |