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authorYann Herklotz <git@ymhg.org>2019-05-10 17:40:57 +0100
committerYann Herklotz <git@ymhg.org>2019-05-10 17:40:57 +0100
commit8241ebad9374187b20ee0fdd43029a2a5ddfbb4e (patch)
tree5b1ef5dd36b07c1e4a29b9049f2bcbb15094a118
parent06c61e705d952679a6200e7d18d2463723fe5878 (diff)
downloadverismith-8241ebad9374187b20ee0fdd43029a2a5ddfbb4e.tar.gz
verismith-8241ebad9374187b20ee0fdd43029a2a5ddfbb4e.zip
Fix but remove the doctests for now
They were not working well with the current printing method. I have to find a way to remove the spaces from the output.
-rw-r--r--src/VeriFuzz/Reduce.hs50
-rw-r--r--verifuzz.cabal24
2 files changed, 38 insertions, 36 deletions
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 48a3c78..df92d99 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -188,14 +188,14 @@ halveExpr = combine contexpr $ traverse halveModExpr
--
-- >>> GenVerilog srcInfo
-- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
+-- m m(y, x);
-- endmodule
-- <BLANKLINE>
-- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- <BLANKLINE>
@@ -203,28 +203,28 @@ halveExpr = combine contexpr $ traverse halveModExpr
-- >>> GenVerilog <$> halveModules srcInfo
-- --- Only try:
-- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- <BLANKLINE>
--
-- >>> GenVerilog srcInfo2
-- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
--- m2 m2(y, x);
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
+-- m m(y, x);
+-- m2 m2(y, x);
-- endmodule
-- <BLANKLINE>
-- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- module m2(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- <BLANKLINE>
@@ -232,27 +232,27 @@ halveExpr = combine contexpr $ traverse halveModExpr
-- >>> GenVerilog <$> halveModules srcInfo2
-- --- Try:
-- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m m(y, x);
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
+-- m m(y, x);
-- endmodule
-- <BLANKLINE>
-- module m(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- <BLANKLINE>
-- --- Then:
-- module top(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
--- m2 m2(y, x);
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
+-- m2 m2(y, x);
-- endmodule
-- <BLANKLINE>
-- module m2(y, x);
--- output wire [(3'h4):(1'h0)] y;
--- input wire [(3'h4):(1'h0)] x;
+-- output wire [(3'h4):(1'h0)] y;
+-- input wire [(3'h4):(1'h0)] x;
-- endmodule
-- <BLANKLINE>
-- <BLANKLINE>
diff --git a/verifuzz.cabal b/verifuzz.cabal
index 9a6b4d8..aaaac7e 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -58,6 +58,7 @@ library
, VeriFuzz.Verilog.Mutate
, VeriFuzz.Verilog.Parser
, VeriFuzz.Verilog.Preprocess
+ , VeriFuzz.Verilog.Quote
, VeriFuzz.Verilog.Token
build-depends: base >=4.7 && <5
, hedgehog >= 0.6 && <0.7
@@ -87,6 +88,7 @@ library
, monad-control >=1.0.2 && <1.1
, gitrev >= 1.3.1 && <1.4
, deepseq >= 1.4.4.0 && <1.5
+ , template-haskell >=2.14.0 && <2.15
default-extensions: OverloadedStrings
executable verifuzz
@@ -125,14 +127,14 @@ test-suite test
, parsec >= 3.1 && < 3.2
default-extensions: OverloadedStrings
-test-suite doctest
- default-language: Haskell2010
- type: exitcode-stdio-1.0
- hs-source-dirs: test
- main-is: Doctest.hs
- other-modules: Build_doctests
- build-depends: base >=4.7 && <5
- , doctest >=0.16 && <0.17
- , Glob >=0.9.3 && <0.11
- , verifuzz
- default-extensions: OverloadedStrings
+--test-suite doctest
+-- default-language: Haskell2010
+-- type: exitcode-stdio-1.0
+-- hs-source-dirs: test
+-- main-is: Doctest.hs
+-- other-modules: Build_doctests
+-- build-depends: base >=4.7 && <5
+-- , doctest >=0.16 && <0.17
+-- , Glob >=0.9.3 && <0.11
+-- , verifuzz
+-- default-extensions: OverloadedStrings