Fix linting warnings

9 files changed, 15 insertions, 17 deletions

diff --git a/app/Main.hs b/app/Main.hs
index b79484a..8719da8 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -15,7 +15,7 @@ main :: IO ()
  --main = sample (arbitrary :: Gen (Circuit Input))
 main = do
   gr <- QC.generate $ rDups <$> QC.resize 30 (randomDAG :: QC.Gen (G.Gr Gate ()))
-  let dot = G.showDot . G.fglToDotString $ G.nemap (\x -> show x) (\_ -> "") gr
+  let dot = G.showDot . G.fglToDotString $ G.nemap show (const "") gr
   writeFile "file.dot" dot
   shelly $ run_ "dot" ["-Tpng", "-o", "file.png", "file.dot"]
   -- T.putStrLn $ generate gr
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 2a82592..00ec88b 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -42,7 +42,7 @@ outputsC c =
 
 genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
 genPortsAST f c =
-  (port . frNode <$> f c)
+  port . frNode <$> f c
   where
     port = Port Wire 1
 
@@ -50,7 +50,7 @@ genPortsAST f c =
 -- assignment expressions.
 genAssignExpr :: Gate -> [Node] -> Maybe Expr
 genAssignExpr g [] = Nothing
-genAssignExpr g (n:[]) = Just . Id $ frNode n
+genAssignExpr g [n] = Just . Id $ frNode n
 genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns
   where
     wire = Id $ frNode n
diff --git a/src/Test/VeriFuzz/Graph/Random.hs b/src/Test/VeriFuzz/Graph/Random.hs
index fa72f2f..9483bdf 100644
--- a/src/Test/VeriFuzz/Graph/Random.hs
+++ b/src/Test/VeriFuzz/Graph/Random.hs
@@ -46,7 +46,7 @@ randomDAG :: (Arbitrary l, Arbitrary e, Eq l, Eq e)
                           -- generate random instances of each node
 randomDAG = do
   list <- QC.infiniteListOf QC.arbitrary
-  l <- QC.infiniteListOf $ aE
+  l <- QC.infiniteListOf aE
   QC.sized (\n -> return . G.mkGraph (nodes list n) $ take (10*n) l)
     where
       nodes l n = zip [0..n] $ take n l
diff --git a/src/Test/VeriFuzz/Simulator/Icarus.hs b/src/Test/VeriFuzz/Simulator/Icarus.hs
index 5a4a12d..156d1fc 100644
--- a/src/Test/VeriFuzz/Simulator/Icarus.hs
+++ b/src/Test/VeriFuzz/Simulator/Icarus.hs
@@ -10,8 +10,6 @@ Portability : POSIX
 Icarus verilog module.
 -}
 
-{-# LANGUAGE QuasiQuotes #-}
-
 module Test.VeriFuzz.Simulator.Icarus where
 
 import           Data.ByteString                 (ByteString)
@@ -25,7 +23,7 @@ import           Test.VeriFuzz.Simulator.General
 import           Test.VeriFuzz.Verilog
 import           Text.Shakespeare.Text           (st)
 
-data Icarus = Icarus { icarusPath :: FilePath }
+newtype Icarus = Icarus { icarusPath :: FilePath }
 
 instance Simulator Icarus where
   toText _ = "iverilog"
diff --git a/src/Test/VeriFuzz/Simulator/Xst.hs b/src/Test/VeriFuzz/Simulator/Xst.hs
index 3372ae0..17efb47 100644
--- a/src/Test/VeriFuzz/Simulator/Xst.hs
+++ b/src/Test/VeriFuzz/Simulator/Xst.hs
@@ -24,7 +24,7 @@ import           Test.VeriFuzz.Verilog.AST
 import           Test.VeriFuzz.Verilog.CodeGen
 import           Text.Shakespeare.Text           (st)
 
-data Xst = Xst { xstPath :: FilePath }
+newtype Xst = Xst { xstPath :: FilePath }
 
 instance Simulator Xst where
   toText _ = "xst"
diff --git a/src/Test/VeriFuzz/Simulator/Yosys.hs b/src/Test/VeriFuzz/Simulator/Yosys.hs
index 778918d..bcded2f 100644
--- a/src/Test/VeriFuzz/Simulator/Yosys.hs
+++ b/src/Test/VeriFuzz/Simulator/Yosys.hs
@@ -25,7 +25,7 @@ import           Test.VeriFuzz.Verilog.AST
 import           Test.VeriFuzz.Verilog.CodeGen
 import           Text.Shakespeare.Text           (st)
 
-data Yosys = Yosys { yosysPath :: FilePath }
+newtype Yosys = Yosys { yosysPath :: FilePath }
 
 instance Simulator Yosys where
   toText _ = "yosys"
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 6f6e930..515987a 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -273,7 +273,7 @@ instance Monoid VerilogSrc where
 traverseExpr :: Traversal' Expr Expr
 traverseExpr _ (Number s v)   = pure $ Number s v
 traverseExpr _ (Id id)        = pure $ Id id
-traverseExpr f (Concat e)     = Concat <$> (sequenceA $ f <$> e)
+traverseExpr f (Concat e)     = Concat <$> sequenceA (f <$> e)
 traverseExpr f (UnOp un e)    = UnOp un <$> f e
 traverseExpr f (BinOp l op r) = BinOp <$> f l <*> pure op <*> f r
 traverseExpr f (Cond c l r)   = Cond <$> f c <*> f l <*> f r
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index 81dfd97..ce6541e 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -33,7 +33,7 @@ showT = T.pack . show
 -- | Map a 'Maybe Stmnt' to 'Text'. If it is 'Just stmnt', the generated
 -- statements are returned. If it is 'Nothing', then @;\n@ is returned.
 defMap :: Maybe Stmnt -> Text
-defMap stat = fromMaybe ";\n" $ genStmnt <$> stat
+defMap = maybe ";\n" genStmnt
 
 -- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered.
 genVerilogSrc :: VerilogSrc -> Text
@@ -55,7 +55,7 @@ genModuleDecl mod =
   where
     ports
       | noIn && noOut = ""
-      | otherwise = "(" <> (comma $ genModPort <$> outIn) <> ")"
+      | otherwise = "(" <> comma (genModPort <$> outIn) <> ")"
     modItems = fold $ genModuleItem <$> mod ^. moduleItems
     noOut = null $ mod ^. modOutPorts
     noIn = null $ mod ^. modInPorts
@@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier id) (Identifier name) conn) =
 genModuleItem (Initial stat) = "initial " <> genStmnt stat
 genModuleItem (Always stat) = "always " <> genStmnt stat
 genModuleItem (Decl dir port) =
-  (fromMaybe "" $ ((<>" ") . genPortDir) <$> dir) <> genPort port <> ";\n"
+  (maybe "" (<>" ") . genPortDir <$> dir) <> genPort port <> ";\n"
 
 -- | Generate continuous assignment
 genContAssign :: ContAssign -> Text
@@ -99,7 +99,7 @@ genContAssign (ContAssign val e) =
   "assign " <> name <> " = " <> expr <> ";\n"
   where
     name = val ^. getIdentifier
-    expr = genExpr $ e
+    expr = genExpr e
 
 -- | Generate 'Expr' to 'Text'.
 genExpr :: Expr -> Text
@@ -189,7 +189,7 @@ genPortType (Reg signed)
 
 genAssign :: Text -> Assign -> Text
 genAssign op (Assign r d e) =
-  genLVal r <> op <> fromMaybe "" (genDelay <$> d) <> genExpr e
+  genLVal r <> op <> maybe "" genDelay d <> genExpr e
 
 genStmnt :: Stmnt -> Text
 genStmnt (TimeCtrl d stat) = genDelay d <> " " <> defMap stat
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index b22fc2c..ab9f0ac 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -33,7 +33,7 @@ findAssign id items =
   safe last . catMaybes $ isAssign <$> items
   where
     isAssign (ModCA (ContAssign val expr))
-      | val == id = Just $ expr
+      | val == id = Just expr
       | otherwise = Nothing
     isAssign _ = Nothing
 
@@ -43,7 +43,7 @@ findAssign id items =
 idTrans :: Identifier -> Expr -> Expr -> Expr
 idTrans i expr (Id id)
   | id == i = expr
-  | otherwise = (Id id)
+  | otherwise = Id id
 idTrans _ _ e = e
 
 -- | Replaces the identifier recursively in an expression.