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authorYann Herklotz <git@yannherklotz.com>2019-09-04 20:15:51 +1000
committerYann Herklotz <git@yannherklotz.com>2019-09-04 20:15:51 +1000
commita2b01b92612a098673ff03890e6e8aef4ceb28ea (patch)
tree15cafe6ba47981938552a4b342a56795251aadc5
parentcccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (diff)
downloadverismith-a2b01b92612a098673ff03890e6e8aef4ceb28ea.tar.gz
verismith-a2b01b92612a098673ff03890e6e8aef4ceb28ea.zip
Renaming to VeriSmith
-rw-r--r--src/VeriSmith.hs (renamed from src/VeriFuzz.hs)0
-rw-r--r--src/VeriSmith/Circuit.hs (renamed from src/VeriFuzz/Circuit.hs)0
-rw-r--r--src/VeriSmith/Circuit/Base.hs (renamed from src/VeriFuzz/Circuit/Base.hs)0
-rw-r--r--src/VeriSmith/Circuit/Gen.hs (renamed from src/VeriFuzz/Circuit/Gen.hs)0
-rw-r--r--src/VeriSmith/Circuit/Internal.hs (renamed from src/VeriFuzz/Circuit/Internal.hs)0
-rw-r--r--src/VeriSmith/Circuit/Random.hs (renamed from src/VeriFuzz/Circuit/Random.hs)0
-rw-r--r--src/VeriSmith/Config.hs (renamed from src/VeriFuzz/Config.hs)0
-rw-r--r--src/VeriSmith/Fuzz.hs (renamed from src/VeriFuzz/Fuzz.hs)0
-rw-r--r--src/VeriSmith/Generate.hs (renamed from src/VeriFuzz/Generate.hs)0
-rw-r--r--src/VeriSmith/Internal.hs (renamed from src/VeriFuzz/Internal.hs)0
-rw-r--r--src/VeriSmith/Reduce.hs (renamed from src/VeriFuzz/Reduce.hs)0
-rw-r--r--src/VeriSmith/Report.hs (renamed from src/VeriFuzz/Report.hs)0
-rw-r--r--src/VeriSmith/Result.hs (renamed from src/VeriFuzz/Result.hs)0
-rw-r--r--src/VeriSmith/Sim.hs (renamed from src/VeriFuzz/Sim.hs)0
-rw-r--r--src/VeriSmith/Sim/Icarus.hs (renamed from src/VeriFuzz/Sim/Icarus.hs)0
-rw-r--r--src/VeriSmith/Sim/Identity.hs (renamed from src/VeriFuzz/Sim/Identity.hs)0
-rw-r--r--src/VeriSmith/Sim/Internal.hs (renamed from src/VeriFuzz/Sim/Internal.hs)0
-rw-r--r--src/VeriSmith/Sim/Quartus.hs (renamed from src/VeriFuzz/Sim/Quartus.hs)0
-rw-r--r--src/VeriSmith/Sim/Template.hs (renamed from src/VeriFuzz/Sim/Template.hs)0
-rw-r--r--src/VeriSmith/Sim/Vivado.hs (renamed from src/VeriFuzz/Sim/Vivado.hs)0
-rw-r--r--src/VeriSmith/Sim/XST.hs (renamed from src/VeriFuzz/Sim/XST.hs)0
-rw-r--r--src/VeriSmith/Sim/Yosys.hs (renamed from src/VeriFuzz/Sim/Yosys.hs)0
-rw-r--r--src/VeriSmith/Verilog.hs (renamed from src/VeriFuzz/Verilog.hs)0
-rw-r--r--src/VeriSmith/Verilog/AST.hs (renamed from src/VeriFuzz/Verilog/AST.hs)0
-rw-r--r--src/VeriSmith/Verilog/BitVec.hs (renamed from src/VeriFuzz/Verilog/BitVec.hs)0
-rw-r--r--src/VeriSmith/Verilog/CodeGen.hs (renamed from src/VeriFuzz/Verilog/CodeGen.hs)0
-rw-r--r--src/VeriSmith/Verilog/Eval.hs (renamed from src/VeriFuzz/Verilog/Eval.hs)0
-rw-r--r--src/VeriSmith/Verilog/Internal.hs (renamed from src/VeriFuzz/Verilog/Internal.hs)0
-rw-r--r--src/VeriSmith/Verilog/Lex.x (renamed from src/VeriFuzz/Verilog/Lex.x)0
-rw-r--r--src/VeriSmith/Verilog/Mutate.hs (renamed from src/VeriFuzz/Verilog/Mutate.hs)0
-rw-r--r--src/VeriSmith/Verilog/Parser.hs (renamed from src/VeriFuzz/Verilog/Parser.hs)0
-rw-r--r--src/VeriSmith/Verilog/Preprocess.hs (renamed from src/VeriFuzz/Verilog/Preprocess.hs)0
-rw-r--r--src/VeriSmith/Verilog/Quote.hs (renamed from src/VeriFuzz/Verilog/Quote.hs)0
-rw-r--r--src/VeriSmith/Verilog/Token.hs (renamed from src/VeriFuzz/Verilog/Token.hs)0
34 files changed, 0 insertions, 0 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriSmith.hs
index 6c1a1b5..6c1a1b5 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriSmith.hs
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriSmith/Circuit.hs
index aee0d57..aee0d57 100644
--- a/src/VeriFuzz/Circuit.hs
+++ b/src/VeriSmith/Circuit.hs
diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriSmith/Circuit/Base.hs
index ddcaf65..ddcaf65 100644
--- a/src/VeriFuzz/Circuit/Base.hs
+++ b/src/VeriSmith/Circuit/Base.hs
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriSmith/Circuit/Gen.hs
index 1c4dd37..1c4dd37 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriSmith/Circuit/Gen.hs
diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/VeriSmith/Circuit/Internal.hs
index b746738..b746738 100644
--- a/src/VeriFuzz/Circuit/Internal.hs
+++ b/src/VeriSmith/Circuit/Internal.hs
diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriSmith/Circuit/Random.hs
index ca8cc26..ca8cc26 100644
--- a/src/VeriFuzz/Circuit/Random.hs
+++ b/src/VeriSmith/Circuit/Random.hs
diff --git a/src/VeriFuzz/Config.hs b/src/VeriSmith/Config.hs
index adc3d19..adc3d19 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriSmith/Config.hs
diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriSmith/Fuzz.hs
index 9331a5e..9331a5e 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriSmith/Fuzz.hs
diff --git a/src/VeriFuzz/Generate.hs b/src/VeriSmith/Generate.hs
index 095baee..095baee 100644
--- a/src/VeriFuzz/Generate.hs
+++ b/src/VeriSmith/Generate.hs
diff --git a/src/VeriFuzz/Internal.hs b/src/VeriSmith/Internal.hs
index 86cb1f7..86cb1f7 100644
--- a/src/VeriFuzz/Internal.hs
+++ b/src/VeriSmith/Internal.hs
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriSmith/Reduce.hs
index c57b457..c57b457 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriSmith/Reduce.hs
diff --git a/src/VeriFuzz/Report.hs b/src/VeriSmith/Report.hs
index fe680c3..fe680c3 100644
--- a/src/VeriFuzz/Report.hs
+++ b/src/VeriSmith/Report.hs
diff --git a/src/VeriFuzz/Result.hs b/src/VeriSmith/Result.hs
index 7bfbf9b..7bfbf9b 100644
--- a/src/VeriFuzz/Result.hs
+++ b/src/VeriSmith/Result.hs
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriSmith/Sim.hs
index f0489d3..f0489d3 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriSmith/Sim.hs
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriSmith/Sim/Icarus.hs
index f104630..f104630 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriSmith/Sim/Icarus.hs
diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/VeriSmith/Sim/Identity.hs
index cac230f..cac230f 100644
--- a/src/VeriFuzz/Sim/Identity.hs
+++ b/src/VeriSmith/Sim/Identity.hs
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriSmith/Sim/Internal.hs
index 017faad..017faad 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriSmith/Sim/Internal.hs
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriSmith/Sim/Quartus.hs
index 6837133..6837133 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriSmith/Sim/Quartus.hs
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriSmith/Sim/Template.hs
index d232420..d232420 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriSmith/Sim/Template.hs
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriSmith/Sim/Vivado.hs
index e8d8f0d..e8d8f0d 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriSmith/Sim/Vivado.hs
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriSmith/Sim/XST.hs
index 30a4b0b..30a4b0b 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriSmith/Sim/XST.hs
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriSmith/Sim/Yosys.hs
index 1f583a8..1f583a8 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriSmith/Sim/Yosys.hs
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriSmith/Verilog.hs
index 6e7851c..6e7851c 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriSmith/Verilog.hs
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriSmith/Verilog/AST.hs
index 78bad45..78bad45 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriSmith/Verilog/AST.hs
diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriSmith/Verilog/BitVec.hs
index dab9e2c..dab9e2c 100644
--- a/src/VeriFuzz/Verilog/BitVec.hs
+++ b/src/VeriSmith/Verilog/BitVec.hs
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriSmith/Verilog/CodeGen.hs
index 1e94472..1e94472 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriSmith/Verilog/CodeGen.hs
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriSmith/Verilog/Eval.hs
index 1ebaa80..1ebaa80 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriSmith/Verilog/Eval.hs
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriSmith/Verilog/Internal.hs
index ed91b12..ed91b12 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriSmith/Verilog/Internal.hs
diff --git a/src/VeriFuzz/Verilog/Lex.x b/src/VeriSmith/Verilog/Lex.x
index 3d1dd8d..3d1dd8d 100644
--- a/src/VeriFuzz/Verilog/Lex.x
+++ b/src/VeriSmith/Verilog/Lex.x
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriSmith/Verilog/Mutate.hs
index 58675e3..58675e3 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriSmith/Verilog/Mutate.hs
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriSmith/Verilog/Parser.hs
index 8d2b729..8d2b729 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriSmith/Verilog/Parser.hs
diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriSmith/Verilog/Preprocess.hs
index c30252b..c30252b 100644
--- a/src/VeriFuzz/Verilog/Preprocess.hs
+++ b/src/VeriSmith/Verilog/Preprocess.hs
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriSmith/Verilog/Quote.hs
index 3815fe6..3815fe6 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriSmith/Verilog/Quote.hs
diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/VeriSmith/Verilog/Token.hs
index 590672e..590672e 100644
--- a/src/VeriFuzz/Verilog/Token.hs
+++ b/src/VeriSmith/Verilog/Token.hs