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| author | Yann Herklotz <git@yannherklotz.com> | 2019-10-25 17:03:51 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-25 17:03:51 +0100 |
| commit | 74d659752eb082371da88abacb9fc4164ca5b931 (patch) | |
| tree | 491d3390c250587ab362f876cea62470e917b8dc | |
| parent | a33c485f49a445d51f7ff5857d081dc0e093f181 (diff) | |
| download | verismith-74d659752eb082371da88abacb9fc4164ca5b931.tar.gz verismith-74d659752eb082371da88abacb9fc4164ca5b931.zip | |
Add comment to code generation
| -rw-r--r-- | src/Verismith/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs index ca48a33..842394d 100644 --- a/src/Verismith/Verilog/CodeGen.hs +++ b/src/Verismith/Verilog/CodeGen.hs @@ -45,7 +45,7 @@ defMap = maybe semi statement -- | Convert the 'Verilog' type to 'Text' so that it can be rendered. verilogSrc :: Verilog -> Doc a -verilogSrc (Verilog modules) = vsep . punctuate line $ moduleDecl <$> modules +verilogSrc (Verilog modules) = vsep . ("// -*- mode: verilog -*-" :) . punctuate line $ moduleDecl <$> modules -- | Generate the 'ModDecl' for a module and convert it to 'Text'. moduleDecl :: ModDecl -> Doc a |