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author | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:52 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:52 +0100 |
commit | 78e70ea4382af2ab093facda0657b7bd3fa2ff01 (patch) | |
tree | 6e87fc85d3365a87c0437c73ab5524434b0e0043 | |
parent | 19955b197a0a70d626c2e3c27dc91aabcb8b3e6a (diff) | |
download | verismith-78e70ea4382af2ab093facda0657b7bd3fa2ff01.tar.gz verismith-78e70ea4382af2ab093facda0657b7bd3fa2ff01.zip |
Formatting files and add result type to front end
-rw-r--r-- | app/Main.hs | 3 | ||||
-rw-r--r-- | src/VeriFuzz.hs | 2 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Icarus.hs | 2 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Quartus.hs | 10 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Vivado.hs | 3 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 3 |
6 files changed, 15 insertions, 8 deletions
diff --git a/app/Main.hs b/app/Main.hs index 3c88e74..4174f99 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -200,8 +200,7 @@ handleOpts :: Opts -> IO () handleOpts (Fuzz out configF _ _) = do config <- getConfig configF _ <- V.runFuzz - [V.defaultYosysSynth, V.defaultVivadoSynth, V.defaultQuartusSynth] - [] + config V.defaultYosys (V.fuzzMultiple 5 (S.fromText out) (V.proceduralSrc "top" config)) return () diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index 88a2a40..f2fb90b 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -19,6 +19,7 @@ module VeriFuzz , module VeriFuzz.Circuit , module VeriFuzz.Sim , module VeriFuzz.Fuzz + , module VeriFuzz.Report ) where @@ -42,6 +43,7 @@ import VeriFuzz.Circuit import VeriFuzz.Config import VeriFuzz.Fuzz import VeriFuzz.Reduce +import VeriFuzz.Report import VeriFuzz.Result import VeriFuzz.Sim import VeriFuzz.Sim.Internal diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index aceb516..ec79340 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -48,7 +48,7 @@ data Icarus = Icarus { icarusPath :: FilePath deriving (Eq) instance Show Icarus where - show _ = "show" + show _ = "iverilog" instance Tool Icarus where toText _ = "iverilog" diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index cac1fb8..0559637 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -54,8 +54,14 @@ runSynthQuartus sim (SourceInfo top src) = do ex (exec "quartus_fit") [top, "--part=5CGXFC7D6F31C6"] ex (exec "quartus_eda") [top, "--simulation", "--tool=vcs"] liftSh $ do - cp (fromText "simulation/vcs" </> fromText top <.> "vo") $ synthOutput sim - run_ "sed" ["-ri", "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", toTextIgnore $ synthOutput sim] + cp (fromText "simulation/vcs" </> fromText top <.> "vo") + $ synthOutput sim + run_ + "sed" + [ "-ri" + , "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;" + , toTextIgnore $ synthOutput sim + ] echoP "Quartus synthesis done" where inpf = "rtl.v" diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index d213a12..6ede8b5 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -47,7 +47,8 @@ runSynthVivado :: Vivado -> SourceInfo -> ResultSh () runSynthVivado sim (SourceInfo top src) = do dir <- liftSh pwd liftSh $ do - writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput sim + writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput + sim writefile "rtl.v" $ genSource src run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) module/;", "-i", "rtl.v"] echoP "Vivado: run" diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index f219e01..f72fb1a 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -66,8 +66,7 @@ runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do out = toTextIgnore $ synthOutput sim runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> ResultSh () -runMaybeSynth (Just sim) srcInfo = - runSynth sim srcInfo +runMaybeSynth (Just sim) srcInfo = runSynth sim srcInfo runMaybeSynth Nothing (SourceInfo _ src) = liftSh . writefile "rtl.v" $ genSource src |