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author | Yann Herklotz <git@ymhg.org> | 2019-04-21 07:19:06 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-21 07:19:06 +0100 |
commit | 8f7d6e4ee2941c592a33510687a724c4c733d403 (patch) | |
tree | 9b8555ff04b7981470362f7e89e4fde6c1f6a103 | |
parent | 220ebcba740e128b0065facbdfd27682ad39e1dd (diff) | |
download | verismith-8f7d6e4ee2941c592a33510687a724c4c733d403.tar.gz verismith-8f7d6e4ee2941c592a33510687a724c4c733d403.zip |
Add new modules to fix Quartus equivalence check
-rw-r--r-- | data/cells_cyclone_v.v | 55 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Quartus.hs | 1 |
2 files changed, 55 insertions, 1 deletions
diff --git a/data/cells_cyclone_v.v b/data/cells_cyclone_v.v index bc70a27..7c2d038 100644 --- a/data/cells_cyclone_v.v +++ b/data/cells_cyclone_v.v @@ -235,4 +235,57 @@ assign o = i, obar = ~i; endmodule -// ========================================================================================== +module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, devclrn, devpor, q ); +// GLOBAL PARAMETER DECLARATION +parameter power_up = "DONT_CARE"; +parameter is_wysiwyg = "false"; +parameter dont_touch = "false"; + + +parameter x_on_violation = "on"; +parameter lpm_type = "dffeas"; + +input d; +input clk; +input ena; +input clrn; +input prn; +input aload; +input asdata; +input sclr; +input sload; +input devclrn; +input devpor; + +output q; + +always @(posedge clk) begin + q <= d; +end + +endmodule + +module cyclonev_clkena ( + inclk, + ena, + enaout, + outclk); + +// leda G_521_3_B off + parameter clock_type = "auto"; + parameter ena_register_mode = "always enabled"; + parameter lpm_type = "cyclonev_clkena"; + parameter ena_register_power_up = "high"; + parameter disable_mode = "low"; + parameter test_syn = "high"; +// leda G_521_3_B on + + input inclk; + input ena; + output enaout; + output outclk; + + assign outclk = ena ? inclk : 1'b0; + assign enaout = ena; + +endmodule //cyclonev_clkena diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index 5bda0be..cac1fb8 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -55,6 +55,7 @@ runSynthQuartus sim (SourceInfo top src) = do ex (exec "quartus_eda") [top, "--simulation", "--tool=vcs"] liftSh $ do cp (fromText "simulation/vcs" </> fromText top <.> "vo") $ synthOutput sim + run_ "sed" ["-ri", "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", toTextIgnore $ synthOutput sim] echoP "Quartus synthesis done" where inpf = "rtl.v" |