Fix used wire check for clk

4 files changed, 32 insertions, 14 deletions

diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs
index e68fc95..f85ab1f 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriFuzz/Fuzz.hs
@@ -121,7 +121,7 @@ synthesis src = do
         .= applyList (uncurry . SynthStatus <$> synth) (fmap swap resTimes)
     liftSh $ inspect resTimes
   where
-    exec a = toolRun ("synthesisis with " <> toText a) . runResultT $ do
+    exec a = toolRun ("synthesis with " <> toText a) . runResultT $ do
         liftSh . mkdir_p . fromText $ toText a
         pop (fromText $ toText a) $ runSynth a src
 
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 4875e7d..fcc8e51 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -111,7 +111,7 @@ instance Traversable Replacement where
 
 -- | Split a list in two halves.
 halve :: Replace [a]
-halve []  = None
+halve []  = Single []
 halve [_] = Single []
 halve l   = Dual a b where (a, b) = splitAt (length l `div` 2) l
 
@@ -254,6 +254,12 @@ exprId (VecSelect   i _) = Just i
 exprId (RangeSelect i _) = Just i
 exprId _                 = Nothing
 
+eventId :: Event -> Maybe Identifier
+eventId (EId i)      = Just i
+eventId (EPosEdge i) = Just i
+eventId (ENegEdge i) = Just i
+eventId _            = Nothing
+
 portToId :: Port -> Identifier
 portToId (Port _ _ _ i) = i
 
@@ -396,16 +402,19 @@ toIds = nub . mapMaybe exprId . concatMap universe
 toIdsConst :: [ConstExpr] -> [Identifier]
 toIdsConst = toIds . fmap constToExpr
 
+toIdsEvent :: [Event] -> [Identifier]
+toIdsEvent = nub . mapMaybe eventId . concatMap universe
+
 allStatIds' :: Statement -> [Identifier]
-allStatIds' s = nub $ assignIds <> otherExpr
+allStatIds' s = nub $ assignIds <> otherExpr <> eventProcessedIds
   where
-    assignIds =
-        toIds
+    assignIds = toIds
             $  (s ^.. stmntBA . assignExpr)
             <> (s ^.. stmntNBA . assignExpr)
             <> (s ^.. forAssign . assignExpr)
             <> (s ^.. forIncr . assignExpr)
     otherExpr = toIds $ (s ^.. forExpr) <> (s ^.. stmntCondExpr)
+    eventProcessedIds = toIdsEvent $ s ^.. statEvent
 
 allStatIds :: Statement -> [Identifier]
 allStatIds s = nub . concat $ allStatIds' <$> universe s
@@ -505,22 +514,22 @@ reduce_ title repl bot eval src = do
     case repl src of
         Single s -> do
             red <- eval s
-            if red then runIf s else return s
+            if red
+                then if cond s then recReduction s else return s
+                else return src
         Dual l r -> do
             red <- eval l
-            if red && cond l
-                then reduce_ title repl bot eval l
+            if red
+                then if cond l then recReduction l else return l
                 else do
                     red' <- eval r
-                    if red' && cond r
-                        then reduce_ title repl bot eval r
-                        else if l < r then return l else return r
+                    if red'
+                        then if cond r then recReduction r else return r
+                        else return src
         None -> return src
   where
-    runIf s = if cond s
-        then reduce_ title repl bot eval s
-        else return s
     cond s = s /= src && not (bot s)
+    recReduction = reduce_ title repl bot eval
 
 -- | Reduce an input to a minimal representation. It follows the reduction
 -- strategy mentioned above.
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 7a654fd..f201064 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -169,6 +169,9 @@ data Event = EId {-# UNPACK #-} !Identifier
            | EComb !Event !Event
            deriving (Eq, Show, Ord, Data)
 
+instance Plated Event where
+    plate = uniplate
+
 -- | Binary operators that are currently supported in the verilog generation.
 data BinaryOperator = BinPlus    -- ^ @+@
                     | BinMinus   -- ^ @-@
diff --git a/test/Reduce.hs b/test/Reduce.hs
index 9c59e48..bc4bbc3 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -52,6 +52,7 @@ module top;
   reg h;
   wire i;
   wire j;
+  wire clk;
   initial d <= a;
 
   always @* begin
@@ -62,6 +63,8 @@ module top;
     end
   end
 
+  always @(posedge clk);
+
   assign b = g;
 endmodule
 |]
@@ -74,6 +77,7 @@ module top;
   reg f;
   reg g;
   reg h;
+  wire clk;
   initial d <= a;
 
   always @* begin
@@ -84,6 +88,8 @@ module top;
     end
   end
 
+  always @(posedge clk);
+
   assign b = g;
 endmodule
 |]