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authorYann Herklotz <ymherklotz@gmail.com>2018-12-29 23:42:18 +0100
committerYann Herklotz <ymherklotz@gmail.com>2018-12-29 23:42:18 +0100
commit40b09529403cf7b7190a45596d36c2f200504988 (patch)
tree9199615ce797d64650a9f4cf8a555a8f6b73c62b
parent97462372591b8bae4eb34a35197c2b606c0c8bd7 (diff)
downloadverismith-40b09529403cf7b7190a45596d36c2f200504988.tar.gz
verismith-40b09529403cf7b7190a45596d36c2f200504988.zip
Add remove duplicates
-rw-r--r--app/Main.hs4
-rw-r--r--src/Test/VeriFuzz/Graph/ASTGen.hs4
-rw-r--r--src/Test/VeriFuzz/Graph/Random.hs20
3 files changed, 20 insertions, 8 deletions
diff --git a/app/Main.hs b/app/Main.hs
index 5cdc245..35c202f 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -17,12 +17,12 @@ instance Gviz.Labellable Gate where
main :: IO ()
--main = sample (arbitrary :: Gen (Circuit Input))
main = do
- gr <- QC.generate $ QC.resize 100 (V.randomDAG :: QC.Gen (G.Gr Gate ()))
+ gr <- QC.generate $ rDups <$> QC.resize 15 (randomDAG :: QC.Gen (G.Gr Gate ()))
let dot = Gviz.graphToDot Gviz.nonClusteredParams . G.emap (const "") $ gr
_ <- Gviz.runGraphviz dot Gviz.Png "output.png"
return ()
-- T.putStrLn $ generate gr
-- g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc))
- -- render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
+ render . genVerilogSrc . addTestBench . nestUpTo 5 . generateAST $ Circuit gr
-- render . genVerilogSrc . addTestBench $ g
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 28dc32a..00eb71d 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -73,11 +73,11 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
nodes = G.labNodes gr
genModuleDeclAST :: Circuit -> ModDecl
-genModuleDeclAST c = ModDecl id Nothing ports items
+genModuleDeclAST c = ModDecl id output ports items
where
id = Identifier "gen_module"
ports = genPortsAST inputsC c
- outPut = safe head $ genPortsAST inputsC c
+ output = Just $ Port (PortNet Wire) "y"
items = genAssignAST c
generateAST :: Circuit -> VerilogSrc
diff --git a/src/Test/VeriFuzz/Graph/Random.hs b/src/Test/VeriFuzz/Graph/Random.hs
index 7f9e3e6..fa72f2f 100644
--- a/src/Test/VeriFuzz/Graph/Random.hs
+++ b/src/Test/VeriFuzz/Graph/Random.hs
@@ -12,11 +12,23 @@ Define the random generation for the directed acyclic graph.
module Test.VeriFuzz.Graph.Random where
-import Data.Graph.Inductive (Graph, LEdge, mkGraph)
+import Data.Graph.Inductive (Context, Graph, LEdge)
+import qualified Data.Graph.Inductive as G
import Data.Graph.Inductive.PatriciaTree (Gr)
+import Data.List (nub)
import Test.QuickCheck (Arbitrary, Gen)
import qualified Test.QuickCheck as QC
+dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b]
+dupFolder cont ns =
+ unique cont : ns
+ where
+ unique (a, b, c, d) = (nub a, b, c, nub d)
+
+-- | Remove duplicates.
+rDups :: (Eq a, Eq b) => Gr a b -> Gr a b
+rDups g = G.buildGr $ G.ufold dupFolder [] g
+
-- | Gen instance to create an arbitrary edge, where the edges are limited by
-- `n` that is passed to it.
arbitraryEdge :: (Arbitrary e) => Int -> Gen (LEdge e)
@@ -29,18 +41,18 @@ arbitraryEdge n = do
with = QC.suchThat $ QC.resize n QC.arbitrary
-- | Gen instance for a random acyclic DAG.
-randomDAG :: (Arbitrary l, Arbitrary e)
+randomDAG :: (Arbitrary l, Arbitrary e, Eq l, Eq e)
=> Gen (Gr l e) -- ^ The generated graph. It uses Arbitrary to
-- generate random instances of each node
randomDAG = do
list <- QC.infiniteListOf QC.arbitrary
l <- QC.infiniteListOf $ aE
- QC.sized (\n -> return . mkGraph (nodes list n) $ take (10*n) l)
+ QC.sized (\n -> return . G.mkGraph (nodes list n) $ take (10*n) l)
where
nodes l n = zip [0..n] $ take n l
aE = QC.sized arbitraryEdge
-- | Generate a random acyclic DAG with an IO instance.
-genRandomDAG :: (Arbitrary l, Arbitrary e)
+genRandomDAG :: (Arbitrary l, Arbitrary e, Eq l, Eq e)
=> IO (Gr l e)
genRandomDAG = QC.generate randomDAG