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authorYann Herklotz <git@ymhg.org>2019-04-17 19:20:56 +0100
committerYann Herklotz <git@ymhg.org>2019-04-17 19:20:56 +0100
commit7053c6117f39d39852b3259c677691b5df6e7c04 (patch)
tree8baa488ca37b6f29da6311e2645c328d87c29d91
parent43ae318ed36dcf4098a8740029bf6b4bf92e4960 (diff)
downloadverismith-7053c6117f39d39852b3259c677691b5df6e7c04.tar.gz
verismith-7053c6117f39d39852b3259c677691b5df6e7c04.zip
Use new fuzzing technique instead of the old function
-rw-r--r--app/Main.hs23
-rw-r--r--src/VeriFuzz.hs33
-rw-r--r--src/VeriFuzz/Config.hs2
-rw-r--r--src/VeriFuzz/Sim.hs4
-rw-r--r--src/VeriFuzz/Verilog.hs2
5 files changed, 36 insertions, 28 deletions
diff --git a/app/Main.hs b/app/Main.hs
index af6e568..bec9e67 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -1,7 +1,6 @@
module Main where
import Control.Concurrent
-import Control.Monad (when)
import Data.Text (Text)
import qualified Data.Text as T
import qualified Data.Text.IO as T
@@ -198,22 +197,14 @@ getConfig :: Maybe FilePath -> IO V.Config
getConfig = maybe (return V.defaultConfig) V.parseConfigFile
handleOpts :: Opts -> IO ()
-handleOpts (Fuzz out configF force keep) = do
- num <- getNumCapabilities
+handleOpts (Fuzz _ configF _ _) = do
config <- getConfig configF
- S.shellyFailDir $ do
- when force . S.rm_rf $ S.fromText out
- S.mkdir_p $ S.fromText out
- vars <-
- sequence
- $ (\x -> myForkIO $ V.runEquivalence (V.procedural "top" config)
- ("test_" <> T.pack (show x))
- out
- keep
- 0
- )
- <$> [1 .. num]
- sequence_ $ takeMVar <$> vars
+ _ <- V.runFuzz
+ [V.defaultYosysSynth, V.defaultVivadoSynth, V.defaultQuartusSynth]
+ []
+ V.defaultYosys
+ (V.fuzz (V.proceduralSrc "top" config))
+ return ()
handleOpts (Generate f c) = do
config <- getConfig c
source <- V.proceduralIO "top" config
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index 18ddf34..88a2a40 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -18,6 +18,7 @@ module VeriFuzz
, module VeriFuzz.Config
, module VeriFuzz.Circuit
, module VeriFuzz.Sim
+ , module VeriFuzz.Fuzz
)
where
@@ -39,6 +40,7 @@ import Shelly
import Shelly.Lifted (liftSh)
import VeriFuzz.Circuit
import VeriFuzz.Config
+import VeriFuzz.Fuzz
import VeriFuzz.Reduce
import VeriFuzz.Result
import VeriFuzz.Sim
@@ -114,7 +116,9 @@ checkEquivalence src dir = shellyFailDir $ do
setenv "VERIFUZZ_ROOT" curr
cd (fromText dir)
catch_sh
- ( (runResultT $ runEquiv defaultYosys defaultYosys (Just defaultVivado) src)
+ ( ( runResultT
+ $ runEquiv defaultYosys defaultYosys (Just defaultVivado) src
+ )
>> return True
)
((\_ -> return False) :: RunFailed -> Sh Bool)
@@ -137,16 +141,23 @@ runEquivalence gm t d k i = do
curr <- toTextIgnore <$> pwd
setenv "VERIFUZZ_ROOT" curr
cd (fromText "output" </> fromText n)
- catch_sh
- (runResultT $ runEquiv defaultYosys defaultYosys (Just defaultVivado) srcInfo
- >> liftSh (echoP "Test OK")
- )
- $ onFailure n
- catch_sh
- (runResultT $ runSim (Icarus "iverilog" "vvp") srcInfo rand
- >>= (\b -> liftSh $ echoP ("RTL Sim: " <> showBS b))
- )
- $ onFailure n
+ _ <-
+ catch_sh
+ ( runResultT
+ $ runEquiv defaultYosys
+ defaultYosys
+ (Just defaultVivado)
+ srcInfo
+ >> liftSh (echoP "Test OK")
+ )
+ $ onFailure n
+ _ <-
+ catch_sh
+ ( runResultT
+ $ runSim (Icarus "iverilog" "vvp") srcInfo rand
+ >>= (\b -> liftSh $ echoP ("RTL Sim: " <> showBS b))
+ )
+ $ onFailure n
cd ".."
unless k . rm_rf $ fromText n
when (i < 5) (runEquivalence gm t d k $ i + 1)
diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs
index ecda495..a2e4497 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriFuzz/Config.hs
@@ -124,7 +124,7 @@ defaultConfig = Config (Probability defModItem defStmnt defExpr)
(Property 20 Nothing 3 2 5)
where
defModItem = ProbModItem 5 1 1
- defStmnt = ProbStatement 0 5 1 1
+ defStmnt = ProbStatement 0 15 1 1
defExpr = ProbExpr 1 1 1 1 1 1 0 1 1
twoKey :: Toml.Piece -> Toml.Piece -> Toml.Key
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs
index b0905b7..0736856 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriFuzz/Sim.hs
@@ -25,6 +25,9 @@ module VeriFuzz.Sim
-- ** XST
, XST(..)
, defaultXST
+ -- ** Quartus
+ , Quartus(..)
+ , defaultQuartus
-- * Equivalence
, runEquiv
-- * Simulation
@@ -37,6 +40,7 @@ where
import VeriFuzz.Sim.Icarus
import VeriFuzz.Sim.Internal
+import VeriFuzz.Sim.Quartus
import VeriFuzz.Sim.Vivado
import VeriFuzz.Sim.XST
import VeriFuzz.Sim.Yosys
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index ae4f82b..4f9fd52 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -16,6 +16,8 @@ module VeriFuzz.Verilog
, parseVerilog
, procedural
, proceduralIO
+ , proceduralSrc
+ , proceduralSrcIO
, randomMod
, GenVerilog(..)
, genSource