Add lens library and extend types for AST

2 files changed, 67 insertions, 8 deletions

diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs
index 897855b..e4d19ec 100644
--- a/src/Test/VeriFuzz/VerilogAST.hs
+++ b/src/Test/VeriFuzz/VerilogAST.hs
@@ -1,13 +1,73 @@
+{-# LANGUAGE TemplateHaskell #-}
+
 module Test.VeriFuzz.VerilogAST where
 
-data ModuleItem = 
+import           Control.Lens
+import           Data.Text    (Text)
+import qualified Data.Text    as T
 
--- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
-data ModuleDecl = ModuleDecl { moduleId   :: Text
-                             , ports      :: [Port]
-                             , moduleItem :: ModuleItem
+type NetLVal = Text
+
+type Identifier = Text
+
+data Number = Number { _numSize :: Int
+                     , _numVal  :: Int
+                     } deriving (Show)
+
+data BinaryOperator = BinAnd
+                    | BinOr
+                    | BinXor
+                    deriving (Show)
+
+data UnaryOperator = UnNot
+                   | UnMinus
+                   deriving (Show)
+
+data Primary = PrimNum Number
+             | PrimId Identifier
+             deriving (Show)
+
+data Expression = PrimExpr Primary
+                | UnPrimExpr { _exprUnOp :: UnaryOperator
+                             , _exprPrim :: Primary
                              }
+                | OpExpr { _exprLhs   :: Expression
+                         , _exprBinOp :: BinaryOperator
+                         , _exprRhs   :: Expression
+                         }
+                | CondExpr { _exprCond  :: Expression
+                           , _exprTrue  :: Expression
+                           , _exprFalse :: Expression
+                           }
+                deriving (Show)
+
+data ContAssign = ContAssign { _contAssignNetLVal :: NetLVal
+                             , _contAssignExpr    :: Expression
+                             } deriving (Show)
+
+data PortDir = Input
+             | Output
+             | InOut
+             deriving (Show)
+
+data Port = Port { _portName :: Identifier
+                 , _portDir  :: PortDir
+                 } deriving (Show)
+
+type ModuleItem = Text
+
+-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
+data ModuleDecl = ModuleDecl { _moduleId   :: Identifier
+                             , _modPorts   :: [Port]
+                             , _moduleItem :: ModuleItem
+                             } deriving (Show)
 
 type Description = ModuleDecl
 
 type SourceText = [Description]
+
+makeLenses ''Number
+makeLenses ''Expression
+makeLenses ''ContAssign
+makeLenses ''Port
+makeLenses ''ModuleDecl
diff --git a/verifuzz.cabal b/verifuzz.cabal
index a5d48b6..3f2e933 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -20,21 +20,20 @@ library
                      , Test.VeriFuzz.Types
                      , Test.VeriFuzz.CodeGen
                      , Test.VeriFuzz.Graph.Random
+                     , Test.VeriFuzz.VerilogAST
   build-depends:       base >= 4.7 && < 5
                      , QuickCheck
                      , fgl
                      , text
                      , mwc-random
                      , random
+                     , lens
 
 executable verifuzz
   hs-source-dirs:      src
   main-is:             Main.hs
   default-language:    Haskell2010
   other-modules:       Test.VeriFuzz
-                     , Test.VeriFuzz.Types
-                     , Test.VeriFuzz.CodeGen
-                     , Test.VeriFuzz.Graph.Random
   build-depends:       base >= 4.7 && < 5
                      , QuickCheck
                      , graphviz