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| author | Yann Herklotz <git@yannherklotz.com> | 2019-05-21 12:00:11 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-21 12:00:27 +0100 |
| commit | dc15e7506096064fcb3fd297b15fc89c83ff32d0 (patch) | |
| tree | 8e846375c62a45a761367f48948e37b24492a9ad | |
| parent | 60e28636ef7f102073c3f3366fdede84a8151f48 (diff) | |
| download | verismith-dc15e7506096064fcb3fd297b15fc89c83ff32d0.tar.gz verismith-dc15e7506096064fcb3fd297b15fc89c83ff32d0.zip | |
Add only identity
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 96a90f9..f4c49be 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -459,7 +459,7 @@ calcRange ps i (Range l r) = eval l - eval r + 1 moduleDef :: Maybe Identifier -> StateGen ModDecl moduleDef top = do name <- moduleName top - portList <- some $ nextPort Wire + portList <- Hog.list (Hog.linear 4 10) $ nextPort Wire mi <- Hog.list (Hog.linear 4 100) modItem ps <- many parameter context <- get |