Add Mutate module to VeriFuzz

3 files changed, 18 insertions, 0 deletions

diff --git a/src/Test/VeriFuzz.hs b/src/Test/VeriFuzz.hs
index 88c7854..8600189 100644
--- a/src/Test/VeriFuzz.hs
+++ b/src/Test/VeriFuzz.hs
@@ -6,6 +6,8 @@ module Test.VeriFuzz
   , module Test.VeriFuzz.CodeGen
     -- * Verilog AST Data Types
   , module Test.VeriFuzz.VerilogAST
+    -- * AST Mutation
+  , module Test.VeriFuzz.Mutate
     -- * Graphs
   , module Test.VeriFuzz.Graph.ASTGen
   , module Test.VeriFuzz.Graph.CodeGen
diff --git a/src/Test/VeriFuzz/Mutate.hs b/src/Test/VeriFuzz/Mutate.hs
new file mode 100644
index 0000000..c483aaa
--- /dev/null
+++ b/src/Test/VeriFuzz/Mutate.hs
@@ -0,0 +1,15 @@
+{-|
+Module      : Test.VeriFuzz.Mutation
+Description : Functions to mutate the Verilog AST.
+Copyright   : (c) Yann Herklotz Grave 2018
+License     : GPL-3
+Maintainer  : ymherklotz@gmail.com
+Stability   : experimental
+Portability : POSIX
+
+Functions to mutate the Verilog AST from "Test.VeriFuzz.VerilogAST" to generate
+more random patterns, such as nesting wires instead of creating new ones.
+-}
+
+module Test.VeriFuzz.Mutate where
+
diff --git a/verifuzz.cabal b/verifuzz.cabal
index 17bea7f..a1b743b 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -21,6 +21,7 @@ library
   exposed-modules:     Test.VeriFuzz
                      , Test.VeriFuzz.Circuit
                      , Test.VeriFuzz.CodeGen
+                     , Test.VeriFuzz.Mutate
                      , Test.VeriFuzz.Graph.ASTGen
                      , Test.VeriFuzz.Graph.CodeGen
                      , Test.VeriFuzz.Graph.Random