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authorYann Herklotz <ymherklotz@gmail.com>2018-12-29 22:29:45 +0100
committerYann Herklotz <ymherklotz@gmail.com>2018-12-29 22:29:45 +0100
commit2c84e82a0263c9bf87cc660a9aabeb5f69828253 (patch)
tree21a92bf7e9852e9f1639b16f913c27d2745307e2 /app
parent08f10a6f6cbc4fc8235beacedd587c56a9534f34 (diff)
downloadverismith-2c84e82a0263c9bf87cc660a9aabeb5f69828253.tar.gz
verismith-2c84e82a0263c9bf87cc660a9aabeb5f69828253.zip
Add new generation method
Diffstat (limited to 'app')
-rw-r--r--app/Main.hs17
1 files changed, 11 insertions, 6 deletions
diff --git a/app/Main.hs b/app/Main.hs
index de3f870..5cdc245 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -1,12 +1,15 @@
module Main where
import qualified Data.Graph.Inductive as G
+import qualified Data.Graph.Inductive.Arbitrary as G
+import qualified Data.Graph.Inductive.PatriciaTree as G
import qualified Data.GraphViz as Gviz
import qualified Data.GraphViz.Attributes.Complete as Gviz
import qualified Data.Text.IO as T
import qualified Data.Text.Lazy as T
import qualified Test.QuickCheck as QC
import Test.VeriFuzz
+import qualified Test.VeriFuzz.Graph.RandomAlt as V
instance Gviz.Labellable Gate where
toLabelValue gate = Gviz.StrLabel . T.pack $ show gate
@@ -14,10 +17,12 @@ instance Gviz.Labellable Gate where
main :: IO ()
--main = sample (arbitrary :: Gen (Circuit Input))
main = do
- --gr <- genRandomDAG 100 :: IO (G.Gr Gate ())
- -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png",
- -- T.putStrLn $ generate gr
- g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc))
- --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
+ gr <- QC.generate $ QC.resize 100 (V.randomDAG :: QC.Gen (G.Gr Gate ()))
+ let dot = Gviz.graphToDot Gviz.nonClusteredParams . G.emap (const "") $ gr
+ _ <- Gviz.runGraphviz dot Gviz.Png "output.png"
+ return ()
+ -- T.putStrLn $ generate gr
+ -- g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc))
+ -- render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
- render . genVerilogSrc . addTestBench $ g
+ -- render . genVerilogSrc . addTestBench $ g