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authorYann Herklotz <ymherklotz@gmail.com>2018-12-29 23:42:18 +0100
committerYann Herklotz <ymherklotz@gmail.com>2018-12-29 23:42:18 +0100
commit40b09529403cf7b7190a45596d36c2f200504988 (patch)
tree9199615ce797d64650a9f4cf8a555a8f6b73c62b /app
parent97462372591b8bae4eb34a35197c2b606c0c8bd7 (diff)
downloadverismith-40b09529403cf7b7190a45596d36c2f200504988.tar.gz
verismith-40b09529403cf7b7190a45596d36c2f200504988.zip
Add remove duplicates
Diffstat (limited to 'app')
-rw-r--r--app/Main.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/app/Main.hs b/app/Main.hs
index 5cdc245..35c202f 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -17,12 +17,12 @@ instance Gviz.Labellable Gate where
main :: IO ()
--main = sample (arbitrary :: Gen (Circuit Input))
main = do
- gr <- QC.generate $ QC.resize 100 (V.randomDAG :: QC.Gen (G.Gr Gate ()))
+ gr <- QC.generate $ rDups <$> QC.resize 15 (randomDAG :: QC.Gen (G.Gr Gate ()))
let dot = Gviz.graphToDot Gviz.nonClusteredParams . G.emap (const "") $ gr
_ <- Gviz.runGraphviz dot Gviz.Png "output.png"
return ()
-- T.putStrLn $ generate gr
-- g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc))
- -- render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
+ render . genVerilogSrc . addTestBench . nestUpTo 5 . generateAST $ Circuit gr
-- render . genVerilogSrc . addTestBench $ g