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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-09 18:42:49 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-09 18:42:49 +0000 |
| commit | 504329c031e4ea56bf58c4396d462ceac16e2032 (patch) | |
| tree | 90b433fa3b8a5fa1001f549192300ff29365aa2a /app | |
| parent | d579ddc3d48cfa8c0efeecf9adb2dd363eef49b1 (diff) | |
| download | verismith-504329c031e4ea56bf58c4396d462ceac16e2032.tar.gz verismith-504329c031e4ea56bf58c4396d462ceac16e2032.zip | |
Adding more examples to main
Diffstat (limited to 'app')
| -rw-r--r-- | app/Main.hs | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/app/Main.hs b/app/Main.hs index 4f42c3f..50ea261 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -37,10 +37,17 @@ runSimulation = do -- shelly $ run_ "dot" ["-Tpng", "-o", "file.png", "file.dot"] let circ = head $ (nestUpTo 5 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription rand <- genRandom 20 - val <- shelly $ runSim (Icarus "iverilog") (initMod circ) rand + val <- shelly $ runSim defaultIcarus (initMod circ) rand putStrLn $ showHex val "" +runEquivalence:: IO () +runEquivalence = do + gr <- QC.generate $ rDups <$> QC.resize 100 (randomDAG :: QC.Gen (G.Gr Gate ())) + let circ = initMod . head $ (nestUpTo 5 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription + shelly . verbosely $ runEquiv defaultYosys defaultYosys (Just defaultXst) circ main :: IO () --main = sample (arbitrary :: Gen (Circuit Input)) -main = runSimulation +main = + -- runEquivalence + runSimulation |