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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 02:31:33 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 02:31:33 +0100 |
| commit | 96d9932a71facce2b31c78fa00fe1adc35169ecb (patch) | |
| tree | 0c6e5aa7b3f96a919749dd11bd69cbfb60a219ef /app | |
| parent | f9b387e371df9c3f91de9da7dd6ac3c4efb58ea0 (diff) | |
| download | verismith-96d9932a71facce2b31c78fa00fe1adc35169ecb.tar.gz verismith-96d9932a71facce2b31c78fa00fe1adc35169ecb.zip | |
Make generation more controlled
Diffstat (limited to 'app')
| -rw-r--r-- | app/Main.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/app/Main.hs b/app/Main.hs index 321b536..de3f870 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -12,12 +12,12 @@ instance Gviz.Labellable Gate where toLabelValue gate = Gviz.StrLabel . T.pack $ show gate main :: IO () ---main = sample (arbitrary :: Gen (Circuit Input)) + --main = sample (arbitrary :: Gen (Circuit Input)) main = do - --gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) --- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", --- T.putStrLn $ generate gr - g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc) - --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr + --gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) + -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", + -- T.putStrLn $ generate gr + g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc)) + --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr render . genVerilogSrc . addTestBench $ g |