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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:19:37 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:19:37 +0100 |
| commit | 984152fb9fe9f01e5dc774b20eb467be551724c1 (patch) | |
| tree | d7c67d5f6e2da5ebdd105dfea371ab129e7e172f /app | |
| parent | b0975b12e655eb5c3920f7be2fa6ac57e18317bf (diff) | |
| download | verismith-984152fb9fe9f01e5dc774b20eb467be551724c1.tar.gz verismith-984152fb9fe9f01e5dc774b20eb467be551724c1.zip | |
Edit main
Diffstat (limited to 'app')
| -rw-r--r-- | app/Main.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/app/Main.hs b/app/Main.hs index 5450b3c..321b536 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -17,7 +17,7 @@ main = do --gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", -- T.putStrLn $ generate gr - g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) - --render . genSourceText . addTestBench . nestUpTo 20 . generateAST $ Circuit gr + g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc) + --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr - render . genSourceText . addTestBench $ g + render . genVerilogSrc . addTestBench $ g |