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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-03 12:27:18 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-03 12:27:18 +0000
commitacb51296f6fc5d7ec5ff91feace09c9f1d0a1fbc (patch)
tree7d39feb43cf6a5eadfff5fd075a435da93387e43 /bugs/minimal_3.v
parent5c6ffb3bb6801ca50608700213385e13dae4ef97 (diff)
downloadverismith-acb51296f6fc5d7ec5ff91feace09c9f1d0a1fbc.tar.gz
verismith-acb51296f6fc5d7ec5ff91feace09c9f1d0a1fbc.zip
Add found bugs
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+module test_module(y, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10);
+output wire [1505:0] y;
+input wire [12:0] w1;
+input wire [2:0] w2;
+input wire [16:0] w3;
+input wire [8:0] w4;
+input wire [15:0] w5;
+input wire [22:0] w6;
+input wire [8:0] w7;
+input wire [16:0] w8;
+input wire [17:0] w9;
+input wire [20:0] w10;
+wire [18:0] w98;
+assign w98 = (~&{((22'h5) ? w4 : w3)});
+assign y = {w98};
+endmodule