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author | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:15:10 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:15:10 +0100 |
commit | 6bbb8ebdd5a95f00ec994c5df5152eab41e39d1c (patch) | |
tree | a090bd217fadd728c3378c9ac02a931dacdeb703 /bugs/vivado/1_generated.v | |
parent | 186bb5f37770c150bd8e601e9761211af6a9c277 (diff) | |
download | verismith-6bbb8ebdd5a95f00ec994c5df5152eab41e39d1c.tar.gz verismith-6bbb8ebdd5a95f00ec994c5df5152eab41e39d1c.zip |
Add vivado bugs
Diffstat (limited to 'bugs/vivado/1_generated.v')
-rw-r--r-- | bugs/vivado/1_generated.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/bugs/vivado/1_generated.v b/bugs/vivado/1_generated.v new file mode 100644 index 0000000..de68529 --- /dev/null +++ b/bugs/vivado/1_generated.v @@ -0,0 +1,31 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 +// Date : Thu Apr 11 19:11:05 2019 +// Host : yann-arch running 64-bit unknown +// Command : write_verilog -force syn_vivado.v +// Design : top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7k70tfbg676-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* use_dsp = "no" *) +(* STRUCTURAL_NETLIST = "yes" *) +module top + (y, + wire0); + output y; + input wire0; + + wire \<const0> ; + wire y; + + GND GND + (.G(\<const0> )); + OBUF y_OBUF_inst + (.I(\<const0> ), + .O(y)); +endmodule |