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authorYann Herklotz <ymherklotz@gmail.com>2019-01-19 12:29:39 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-01-19 12:29:39 +0000
commitd5605683a5e927393b89e171306e5d2027016594 (patch)
treecc679736124ecf72979b3a88587c2242719520d6 /data/cells_cmos.v
parent983669aa390c4cc1aaf6e4bee914d1a7de9a58e4 (diff)
downloadverismith-d5605683a5e927393b89e171306e5d2027016594.tar.gz
verismith-d5605683a5e927393b89e171306e5d2027016594.zip
Add data folder with extra modules
These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available
Diffstat (limited to 'data/cells_cmos.v')
-rw-r--r--data/cells_cmos.v38
1 files changed, 38 insertions, 0 deletions
diff --git a/data/cells_cmos.v b/data/cells_cmos.v
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+
+module NOT(A, Y);
+input A;
+output Y;
+assign Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+ Q <= D;
+endmodule
+
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+ if (S)
+ Q <= 1'b1;
+ else if (R)
+ Q <= 1'b0;
+ else
+ Q <= D;
+endmodule
+