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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 12:29:39 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 12:29:39 +0000 |
commit | d5605683a5e927393b89e171306e5d2027016594 (patch) | |
tree | cc679736124ecf72979b3a88587c2242719520d6 /data/cells_verific.v | |
parent | 983669aa390c4cc1aaf6e4bee914d1a7de9a58e4 (diff) | |
download | verismith-d5605683a5e927393b89e171306e5d2027016594.tar.gz verismith-d5605683a5e927393b89e171306e5d2027016594.zip |
Add data folder with extra modules
These modules are required for comparing modules that are generated by
synthesising in different simulators, as they will each synthesise to specific
hardware with assumptions on what is available
Diffstat (limited to 'data/cells_verific.v')
-rw-r--r-- | data/cells_verific.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/data/cells_verific.v b/data/cells_verific.v new file mode 100644 index 0000000..6d0ad2d --- /dev/null +++ b/data/cells_verific.v @@ -0,0 +1,14 @@ +module VERIFIC_FADD (cin, a, b, cout, o); + input cin, a, b; + output cout, o; + assign {cout, o} = cin + a + b; +endmodule + +module VERIFIC_DFFRS (clk, s, r, d, q); + input clk, d, s, r; + output reg q ; + always @(posedge clk, posedge s, posedge r) + if (r) q <= 0; + else if (s) q <= 1; + else q <= d; +endmodule |