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authorYann Herklotz <ymherklotz@gmail.com>2019-01-19 12:29:39 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-01-19 12:29:39 +0000
commitd5605683a5e927393b89e171306e5d2027016594 (patch)
treecc679736124ecf72979b3a88587c2242719520d6 /data/cells_verific.v
parent983669aa390c4cc1aaf6e4bee914d1a7de9a58e4 (diff)
downloadverismith-d5605683a5e927393b89e171306e5d2027016594.tar.gz
verismith-d5605683a5e927393b89e171306e5d2027016594.zip
Add data folder with extra modules
These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available
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diff --git a/data/cells_verific.v b/data/cells_verific.v
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+module VERIFIC_FADD (cin, a, b, cout, o);
+ input cin, a, b;
+ output cout, o;
+ assign {cout, o} = cin + a + b;
+endmodule
+
+module VERIFIC_DFFRS (clk, s, r, d, q);
+ input clk, d, s, r;
+ output reg q ;
+ always @(posedge clk, posedge s, posedge r)
+ if (r) q <= 0;
+ else if (s) q <= 1;
+ else q <= d;
+endmodule