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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:52:15 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:52:15 +0100 |
| commit | 6776d38b11186e97101995eb2c071096cc1d648b (patch) | |
| tree | 7de0d5ac87ffff9d044562ce8626fa7aadaefce9 /data/cells_yosys.v | |
| parent | a640c7e87b0891402c5e51d8b96cac91d6ab1570 (diff) | |
| download | verismith-6776d38b11186e97101995eb2c071096cc1d648b.tar.gz verismith-6776d38b11186e97101995eb2c071096cc1d648b.zip | |
Add missing modules when using always blocks
Diffstat (limited to 'data/cells_yosys.v')
| -rw-r--r-- | data/cells_yosys.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/data/cells_yosys.v b/data/cells_yosys.v new file mode 100644 index 0000000..48f9c66 --- /dev/null +++ b/data/cells_yosys.v @@ -0,0 +1,13 @@ +// Taken from yosys verilog files. + +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule |