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author | Yann Herklotz <git@yannherklotz.com> | 2019-07-23 22:41:01 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-23 22:42:23 +0200 |
commit | 0cfe5e5484dbe30fb52ff0ea5e799313a734a9c6 (patch) | |
tree | fc58e4b706502fd2be7db5f1c62cf264f218bb53 /default.nix | |
parent | 992e91427fccff43f8ab1944131b8f62f9328f0d (diff) | |
download | verismith-0cfe5e5484dbe30fb52ff0ea5e799313a734a9c6.tar.gz verismith-0cfe5e5484dbe30fb52ff0ea5e799313a734a9c6.zip |
[Fix #52] Correctly resize the modules
This was fixed by taking out the clock and wiring it separately as it was
shifting all the assignments.
Diffstat (limited to 'default.nix')
0 files changed, 0 insertions, 0 deletions