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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-10-28 21:08:10 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-10-28 21:10:20 +0000 |
commit | 4fd1105b865e5b20ef801c53bcefbd7a7d5474f0 (patch) | |
tree | 31069b8e72de575f2892089889704d225cbfa98e /src/Main.hs | |
parent | 62fffd351e92b96ad9ae0c88e6b7d59775594ac3 (diff) | |
download | verismith-4fd1105b865e5b20ef801c53bcefbd7a7d5474f0.tar.gz verismith-4fd1105b865e5b20ef801c53bcefbd7a7d5474f0.zip |
Initial commit
Diffstat (limited to 'src/Main.hs')
-rw-r--r-- | src/Main.hs | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/Main.hs b/src/Main.hs new file mode 100644 index 0000000..e25986c --- /dev/null +++ b/src/Main.hs @@ -0,0 +1,28 @@ +module Main where + +import Data.Bits + +newtype Input = Input { getInput :: Bool } + deriving (Show) + +data Gate = And + | Or + | Xor + | Nand + | Nor + deriving (Show) + +data Circuit = In Input + | Node Gate Circuit Circuit + deriving (Show) + +eval :: Circuit -> Bool +eval (In val) = getInput val +eval (Node And c1 c2) = eval c1 .&. eval c2 +eval (Node Or c1 c2) = eval c1 .|. eval c2 +eval (Node Xor c1 c2) = eval c1 `xor` eval c2 +eval (Node Nand c1 c2) = complement $ eval c1 .&. eval c2 +eval (Node Nor c1 c2) = complement $ eval c1 .|. eval c2 + +main :: IO () +main = print . eval $ Node And (In . Input $ True) (In . Input $ True) |