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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:18 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:18 +0100 |
| commit | 3b5b7e33033799ab1eb2289615a2c96b6329cba4 (patch) | |
| tree | 08d43b024daf99cfc8ec8f82bc223a9a04f83681 /src/Test/VeriFuzz/Graph/ASTGen.hs | |
| parent | 5243210a4c16a7349b59a964072c4effb3aea30a (diff) | |
| download | verismith-3b5b7e33033799ab1eb2289615a2c96b6329cba4.tar.gz verismith-3b5b7e33033799ab1eb2289615a2c96b6329cba4.zip | |
Fix imports and cabal file
Diffstat (limited to 'src/Test/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index f1ac88a..5382123 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -18,7 +18,7 @@ import Data.Maybe (catMaybes) import qualified Data.Text as T import Test.VeriFuzz.Circuit import Test.VeriFuzz.Internal.Gen -import Test.VeriFuzz.VerilogAST +import Test.VeriFuzz.Verilog.AST -- | Converts a 'Node' to an 'Identifier'. frNode :: Node -> Identifier @@ -73,5 +73,5 @@ genModuleDeclAST c = ModDecl id ports items ports = genPortsAST c items = genAssignAST c -generateAST :: Circuit -> SourceText -generateAST c = SourceText [Description $ genModuleDeclAST c] +generateAST :: Circuit -> VerilogSrc +generateAST c = VerilogSrc [Description $ genModuleDeclAST c] |