Large refactor

2 files changed, 9 insertions, 9 deletions

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 3c000ea..2a82592 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -44,16 +44,16 @@ genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
 genPortsAST f c =
   (port . frNode <$> f c)
   where
-    port = Port (PortNet Wire) 1
+    port = Port Wire 1
 
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
-genAssignExpr :: Gate -> [Node] -> Maybe Expression
+genAssignExpr :: Gate -> [Node] -> Maybe Expr
 genAssignExpr g [] = Nothing
-genAssignExpr g (n:[]) = Just . PrimExpr . PrimId $ frNode n
-genAssignExpr g (n:ns) = OpExpr wire op <$> genAssignExpr g ns
+genAssignExpr g (n:[]) = Just . Id $ frNode n
+genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns
   where
-    wire = PrimExpr . PrimId $ frNode n
+    wire = Id $ frNode n
     op = fromGate g
 
 -- | Generate the continuous assignment AST for a particular node. If it does
@@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items
   where
     id = Identifier "gen_module"
     ports = genPortsAST inputsC c
-    output = [Port (PortNet Wire) 1 "y"]
+    output = [Port Wire 1 "y"]
     items = genAssignAST c
 
 generateAST :: Circuit -> VerilogSrc
diff --git a/src/Test/VeriFuzz/Graph/CodeGen.hs b/src/Test/VeriFuzz/Graph/CodeGen.hs
index 64abb0a..eaa109e 100644
--- a/src/Test/VeriFuzz/Graph/CodeGen.hs
+++ b/src/Test/VeriFuzz/Graph/CodeGen.hs
@@ -35,8 +35,8 @@ statList g n = toStr <$> safe tail n
 lastEl :: [Node] -> Maybe Text
 lastEl n = fromNode <$> safe head n
 
-toStatement :: (Graph gr) => gr Gate e -> LNode Gate -> Text
-toStatement graph (n, g) =
+toStmnt :: (Graph gr) => gr Gate e -> LNode Gate -> Text
+toStmnt graph (n, g) =
   fromMaybe empty $ Just "  assign " <> Just (fromNode n)
   <> Just " = " <> statList g nodeL <> lastEl nodeL <> Just ";\n"
   where
@@ -48,7 +48,7 @@ generate graph =
   <> fromList (imap "  input wire " ",\n" inp)
   <> sep ",\n" (imap "  output wire " "" out)
   <> ");\n"
-  <> fromList (toStatement graph <$> labNodes graph)
+  <> fromList (toStmnt graph <$> labNodes graph)
   <> "endmodule\n\nmodule main;\n  initial\n    begin\n      "
   <> "$display(\"Hello, world\");\n      $finish;\n    "
   <> "end\nendmodule"