diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 01:56:39 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 01:56:39 +0100 |
| commit | 5db743f5343e874dfeab2e4f81ee98550ce8ef49 (patch) | |
| tree | 4b54ac492f1384bfd39b2346ce92d42f2c40f1cd /src/Test/VeriFuzz/Helpers.hs | |
| parent | f0cc5bb8865b039b18bdc89e81df9bad72e0bdb5 (diff) | |
| download | verismith-5db743f5343e874dfeab2e4f81ee98550ce8ef49.tar.gz verismith-5db743f5343e874dfeab2e4f81ee98550ce8ef49.zip | |
Changes to the API
Diffstat (limited to 'src/Test/VeriFuzz/Helpers.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Helpers.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/Test/VeriFuzz/Helpers.hs b/src/Test/VeriFuzz/Helpers.hs index 6632938..6643683 100644 --- a/src/Test/VeriFuzz/Helpers.hs +++ b/src/Test/VeriFuzz/Helpers.hs @@ -18,10 +18,10 @@ import qualified Data.Text import Test.VeriFuzz.Verilog.AST regDecl :: Text -> ModItem -regDecl = Decl . Port Nothing (Just $ Reg False) . Identifier +regDecl = Decl . Port (Reg False) . Identifier wireDecl :: Text -> ModItem -wireDecl = Decl . Port Nothing (Just $ PortNet Wire) . Identifier +wireDecl = Decl . Port (PortNet Wire) . Identifier modConn :: Text -> ModConn modConn = ModConn . PrimExpr . PrimId . Identifier @@ -32,22 +32,22 @@ numExpr = ((PrimExpr . PrimNum) .) . Number -- | Create an empty module. emptyMod :: ModDecl -emptyMod = ModDecl (Identifier "") [] [] +emptyMod = ModDecl "" Nothing [] [] -- | Set a module name for a module declaration. setModName :: Text -> ModDecl -> ModDecl setModName str = moduleId .~ Identifier str --- | Add a port to the module declaration. +-- | Add a input port to the module declaration. addModPort :: Port -> ModDecl -> ModDecl -addModPort port = modPorts %~ (:) port +addModPort port = modInPorts %~ (:) port addDescription :: Description -> VerilogSrc -> VerilogSrc addDescription desc = getVerilogSrc %~ (:) desc testBench :: ModDecl testBench = - ModDecl "main" [] + ModDecl "main" Nothing [] [ regDecl "a" , regDecl "b" , wireDecl "c" |