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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:29 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:29 +0100 |
commit | fedd3efbe770630fc355223c5ced3faa54f435e5 (patch) | |
tree | e4d5d69ed045a7a69881309ceb873b52fca7f882 /src/Test/VeriFuzz/Simulator/Xst.hs | |
parent | 3b5b7e33033799ab1eb2289615a2c96b6329cba4 (diff) | |
download | verismith-fedd3efbe770630fc355223c5ced3faa54f435e5.tar.gz verismith-fedd3efbe770630fc355223c5ced3faa54f435e5.zip |
Add simulator module
Diffstat (limited to 'src/Test/VeriFuzz/Simulator/Xst.hs')
-rw-r--r-- | src/Test/VeriFuzz/Simulator/Xst.hs | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Simulator/Xst.hs b/src/Test/VeriFuzz/Simulator/Xst.hs new file mode 100644 index 0000000..cfa229d --- /dev/null +++ b/src/Test/VeriFuzz/Simulator/Xst.hs @@ -0,0 +1,52 @@ +{-| +Module : Test.VeriFuzz.Simulator.Xst +Description : Xst (ise) simulator implementation. +Copyright : (c) Yann Herklotz Grave 2018 +License : GPL-3 +Maintainer : ymherklotz@gmail.com +Stability : experimental +Portability : POSIX + +Xst (ise) simulator implementation. +-} + +{-# LANGUAGE QuasiQuotes #-} + +module Test.VeriFuzz.Simulator.Xst where + +import Control.Lens hiding ((<.>)) +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) +import Shelly +import Test.VeriFuzz.Simulator.General +import Test.VeriFuzz.Verilog.AST +import Test.VeriFuzz.Verilog.CodeGen +import Text.Shakespeare.Text (st) + +data Xst = Xst { xstPath :: FilePath } + +instance Simulator Xst where + toText _ = "xst" + +instance Synthesize Xst where + runSynth = runSynthXst + +runSynthXst :: Xst -> ModDecl -> FilePath -> Sh () +runSynthXst sim mod outf = do + writefile xstFile [st|run +-ifn #{modName}.prj -ofn #{modName} -p artix7 -top #{modName} +-iobuf NO -ram_extract NO -rom_extract NO -use_dsp48 NO +-fsm_extract YES -fsm_encoding Auto +-change_error_to_warning "HDLCompiler:226 HDLCompiler:1832" +|] + writefile prjFile [st|verilog work "#{modName}.v"|] + writefile vFile $ genSource mod + timeout_ "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" ["-ifn", toTextIgnore xstFile] + run_ "netgen" ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", "output.v"] + where + modName = mod ^. moduleId . getIdentifier + modFile = fromText modName + xstFile = modFile <.> "xst" + prjFile = modFile <.> "prj" + vFile = modFile <.> "v" |