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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 12:44:42 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 12:44:42 +0100 |
| commit | 619965e928c10caf6fe430cf09c9bc09352ba071 (patch) | |
| tree | 15598c0ab48ee70ce7cbabca1d0b2411d8eb341d /src/Test/VeriFuzz/Verilog/AST.hs | |
| parent | 380b91b8ec012e75d0acffa2635e77afe887d461 (diff) | |
| download | verismith-619965e928c10caf6fe430cf09c9bc09352ba071.tar.gz verismith-619965e928c10caf6fe430cf09c9bc09352ba071.zip | |
Add direction to Decl and add doctest
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 33ccdb4..3ae595f 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -189,7 +189,9 @@ data ModItem = ModCA ContAssign } | Initial Statement | Always Statement - | Decl Port + | Decl { declDir :: Maybe PortDir + , declPort :: Port + } deriving (Show, Eq, Ord) -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' @@ -365,7 +367,7 @@ instance QC.Arbitrary ModItem where , ModInst <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary , Initial <$> QC.arbitrary , Always <$> (EventCtrl <$> QC.arbitrary <*> QC.arbitrary) - , Decl <$> QC.arbitrary + , Decl <$> pure Nothing <*> QC.arbitrary ] instance QC.Arbitrary ModDecl where |