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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 15:35:04 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 15:35:04 +0100 |
commit | 5e3abd02be92f801a86d17501d82b22c644946b7 (patch) | |
tree | 1f7490edd44ded06279ce77b56e618c567a9f79e /src/Test/VeriFuzz/Verilog/AST.hs | |
parent | 6fbe229217ef7f9d74357028b325313b8551198c (diff) | |
download | verismith-5e3abd02be92f801a86d17501d82b22c644946b7.tar.gz verismith-5e3abd02be92f801a86d17501d82b22c644946b7.zip |
Remove Monoid instance for LVal, as it does not quite fit
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/AST.hs')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index b643db5..4f2c52d 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -71,15 +71,6 @@ data LVal = RegId Identifier | RegConcat { _regConc :: [Expr] } deriving (Eq) -instance Semigroup LVal where - (RegConcat a) <> (RegConcat b) = RegConcat $ a <> b - (RegConcat a) <> b = RegConcat $ a <> [b] - a <> (RegConcat b) = RegConcat $ a : b - a <> b = RegConcat [a, b] - -instance Monoid LVal where - mempty = RegConcat [] - -- | Binary operators that are currently supported in the verilog generation. data BinaryOperator = BinPlus -- ^ @+@ | BinMinus -- ^ @-@ |