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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:11 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:11 +0100 |
commit | b25eee73ce7cf8270ccf633443cee88040eaca67 (patch) | |
tree | 8afea5d9f94147add720f650a878a34eb73750a5 /src/Test/VeriFuzz/Verilog/Helpers.hs | |
parent | 40b09529403cf7b7190a45596d36c2f200504988 (diff) | |
download | verismith-b25eee73ce7cf8270ccf633443cee88040eaca67.tar.gz verismith-b25eee73ce7cf8270ccf633443cee88040eaca67.zip |
Move helper functions
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/Helpers.hs | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs new file mode 100644 index 0000000..d4a7c9c --- /dev/null +++ b/src/Test/VeriFuzz/Verilog/Helpers.hs @@ -0,0 +1,76 @@ +{-| +Module : Test.VeriFuzz.VeriFuzz.Helpers +Description : Defaults and common functions. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Defaults and common functions. +-} + +module Test.VeriFuzz.VeriFuzz.Helpers where + +import Control.Lens +import Data.Text (Text) +import qualified Data.Text +import Test.VeriFuzz.Verilog.AST + +regDecl :: Text -> ModItem +regDecl = Decl . Port (Reg False) . Identifier + +wireDecl :: Text -> ModItem +wireDecl = Decl . Port (PortNet Wire) . Identifier + +modConn :: Text -> ModConn +modConn = ModConn . PrimExpr . PrimId . Identifier + +-- | Create a number expression which will be stored in a primary expression. +numExpr :: Int -> Int -> Expression +numExpr = ((PrimExpr . PrimNum) .) . Number + +-- | Create an empty module. +emptyMod :: ModDecl +emptyMod = ModDecl "" Nothing [] [] + +-- | Set a module name for a module declaration. +setModName :: Text -> ModDecl -> ModDecl +setModName str = moduleId .~ Identifier str + +-- | Add a input port to the module declaration. +addModPort :: Port -> ModDecl -> ModDecl +addModPort port = modInPorts %~ (:) port + +addDescription :: Description -> VerilogSrc -> VerilogSrc +addDescription desc = getVerilogSrc %~ (:) desc + +testBench :: ModDecl +testBench = + ModDecl "main" Nothing [] + [ regDecl "a" + , regDecl "b" + , wireDecl "c" + , ModInst "and" "and_gate" + [ modConn "c" + , modConn "a" + , modConn "b" + ] + , Initial $ SeqBlock + [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1 + , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1 + -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" + -- [ ExprStr "%d & %d = %d" + -- , PrimExpr $ PrimId "a" + -- , PrimExpr $ PrimId "b" + -- , PrimExpr $ PrimId "c" + -- ] + -- , SysTaskEnable $ Task "finish" [] + ] + ] + +addTestBench :: VerilogSrc -> VerilogSrc +addTestBench = addDescription $ Description testBench + +defaultPort :: Identifier -> Port +defaultPort = Port (PortNet Wire) 1 |