diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 01:56:39 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 01:56:39 +0100 |
| commit | 5db743f5343e874dfeab2e4f81ee98550ce8ef49 (patch) | |
| tree | 4b54ac492f1384bfd39b2346ce92d42f2c40f1cd /src/Test/VeriFuzz/Verilog/Mutate.hs | |
| parent | f0cc5bb8865b039b18bdc89e81df9bad72e0bdb5 (diff) | |
| download | verismith-5db743f5343e874dfeab2e4f81ee98550ce8ef49.tar.gz verismith-5db743f5343e874dfeab2e4f81ee98550ce8ef49.zip | |
Changes to the API
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 66e56a1..6731b65 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -21,7 +21,11 @@ import Test.VeriFuzz.Verilog.AST -- | Return if the 'Identifier' is in a 'ModDecl'. inPort :: Identifier -> ModDecl -> Bool -inPort id mod = any (\a -> a ^. portName == id) $ mod ^. modPorts +inPort id mod = inInput || inOutput + where + inInput = any (\a -> a ^. portName == id) $ mod ^. modInPorts + inOutput = fromMaybe False . safe head $ (==id) <$> + mod ^.. modOutPort . _Just . portName -- | Find the last assignment of a specific wire/reg to an expression, and -- returns that expression. |