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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:35 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:35 +0100 |
| commit | 2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0 (patch) | |
| tree | e3aa69d19c40261a42a25ee8e5ec860d896919eb /src/Test/VeriFuzz/Verilog/Mutate.hs | |
| parent | b25eee73ce7cf8270ccf633443cee88040eaca67 (diff) | |
| download | verismith-2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0.tar.gz verismith-2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0.zip | |
[Fix #14] Add size to Port type
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 6731b65..6993fef 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -82,3 +82,8 @@ nestUpTo i src = instantiateMod :: ModDecl -> ModDecl -> ModDecl instantiateMod mod main = main + +-- | Initialise all the inputs and outputs to a module. +initMod :: ModDecl -> ModDecl +initMod mod = + mod |