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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 12:21:14 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 12:21:35 +0100 |
| commit | 380b91b8ec012e75d0acffa2635e77afe887d461 (patch) | |
| tree | 6e8531f92536f4bdc7565c9528c38a108b30adcd /src/Test/VeriFuzz/Verilog/Mutate.hs | |
| parent | f785b208f4857571a952c0befde58a7b4c37b0dc (diff) | |
| download | verismith-380b91b8ec012e75d0acffa2635e77afe887d461.tar.gz verismith-380b91b8ec012e75d0acffa2635e77afe887d461.zip | |
[Fix #17] Add size to ports
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 258af84..4c032e7 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -82,8 +82,8 @@ nestUpTo i src = -- -- >>> SrcShow $ instantiateMod (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] []) (ModDecl "main" [] [] []) -- module main; --- wire y; --- reg x; +-- wire [4:0] y; +-- reg [4:0] x; -- endmodule -- <BLANKLINE> instantiateMod :: ModDecl -> ModDecl -> ModDecl |