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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 14:48:54 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 14:48:54 +0100 |
commit | fd2963cae60c87aa3bcf382829cb7c44e6e0c2ae (patch) | |
tree | fdb170affd1b7f727ca057587f01850729a36fd8 /src/Test/VeriFuzz/Verilog | |
parent | 99d2932e1b4357f4e0aa303a29d08bfd81977a9e (diff) | |
download | verismith-fd2963cae60c87aa3bcf382829cb7c44e6e0c2ae.tar.gz verismith-fd2963cae60c87aa3bcf382829cb7c44e6e0c2ae.zip |
Fix linting warnings
Diffstat (limited to 'src/Test/VeriFuzz/Verilog')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 2 | ||||
-rw-r--r-- | src/Test/VeriFuzz/Verilog/CodeGen.hs | 10 | ||||
-rw-r--r-- | src/Test/VeriFuzz/Verilog/Mutate.hs | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 6f6e930..515987a 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -273,7 +273,7 @@ instance Monoid VerilogSrc where traverseExpr :: Traversal' Expr Expr traverseExpr _ (Number s v) = pure $ Number s v traverseExpr _ (Id id) = pure $ Id id -traverseExpr f (Concat e) = Concat <$> (sequenceA $ f <$> e) +traverseExpr f (Concat e) = Concat <$> sequenceA (f <$> e) traverseExpr f (UnOp un e) = UnOp un <$> f e traverseExpr f (BinOp l op r) = BinOp <$> f l <*> pure op <*> f r traverseExpr f (Cond c l r) = Cond <$> f c <*> f l <*> f r diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs index 81dfd97..ce6541e 100644 --- a/src/Test/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs @@ -33,7 +33,7 @@ showT = T.pack . show -- | Map a 'Maybe Stmnt' to 'Text'. If it is 'Just stmnt', the generated -- statements are returned. If it is 'Nothing', then @;\n@ is returned. defMap :: Maybe Stmnt -> Text -defMap stat = fromMaybe ";\n" $ genStmnt <$> stat +defMap = maybe ";\n" genStmnt -- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered. genVerilogSrc :: VerilogSrc -> Text @@ -55,7 +55,7 @@ genModuleDecl mod = where ports | noIn && noOut = "" - | otherwise = "(" <> (comma $ genModPort <$> outIn) <> ")" + | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" modItems = fold $ genModuleItem <$> mod ^. moduleItems noOut = null $ mod ^. modOutPorts noIn = null $ mod ^. modInPorts @@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier id) (Identifier name) conn) = genModuleItem (Initial stat) = "initial " <> genStmnt stat genModuleItem (Always stat) = "always " <> genStmnt stat genModuleItem (Decl dir port) = - (fromMaybe "" $ ((<>" ") . genPortDir) <$> dir) <> genPort port <> ";\n" + (maybe "" (<>" ") . genPortDir <$> dir) <> genPort port <> ";\n" -- | Generate continuous assignment genContAssign :: ContAssign -> Text @@ -99,7 +99,7 @@ genContAssign (ContAssign val e) = "assign " <> name <> " = " <> expr <> ";\n" where name = val ^. getIdentifier - expr = genExpr $ e + expr = genExpr e -- | Generate 'Expr' to 'Text'. genExpr :: Expr -> Text @@ -189,7 +189,7 @@ genPortType (Reg signed) genAssign :: Text -> Assign -> Text genAssign op (Assign r d e) = - genLVal r <> op <> fromMaybe "" (genDelay <$> d) <> genExpr e + genLVal r <> op <> maybe "" genDelay d <> genExpr e genStmnt :: Stmnt -> Text genStmnt (TimeCtrl d stat) = genDelay d <> " " <> defMap stat diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index b22fc2c..ab9f0ac 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -33,7 +33,7 @@ findAssign id items = safe last . catMaybes $ isAssign <$> items where isAssign (ModCA (ContAssign val expr)) - | val == id = Just $ expr + | val == id = Just expr | otherwise = Nothing isAssign _ = Nothing @@ -43,7 +43,7 @@ findAssign id items = idTrans :: Identifier -> Expr -> Expr -> Expr idTrans i expr (Id id) | id == i = expr - | otherwise = (Id id) + | otherwise = Id id idTrans _ _ e = e -- | Replaces the identifier recursively in an expression. |