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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-29 18:54:18 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-29 18:54:18 +0000 |
commit | 451746e7916914d7b1731ef2f4dfd966557bd0f9 (patch) | |
tree | d518e62c5b299540d7b8bc010a888db8f12327fc /src/Test/VeriFuzz | |
parent | ae47b703bdea3d6c5d3e3af49b178527350aa38e (diff) | |
download | verismith-451746e7916914d7b1731ef2f4dfd966557bd0f9.tar.gz verismith-451746e7916914d7b1731ef2f4dfd966557bd0f9.zip |
Add Verilog AST
Diffstat (limited to 'src/Test/VeriFuzz')
-rw-r--r-- | src/Test/VeriFuzz/VerilogAST.hs | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs new file mode 100644 index 0000000..897855b --- /dev/null +++ b/src/Test/VeriFuzz/VerilogAST.hs @@ -0,0 +1,13 @@ +module Test.VeriFuzz.VerilogAST where + +data ModuleItem = + +-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' +data ModuleDecl = ModuleDecl { moduleId :: Text + , ports :: [Port] + , moduleItem :: ModuleItem + } + +type Description = ModuleDecl + +type SourceText = [Description] |