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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-25 13:24:32 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-25 13:24:32 +0100 |
commit | 5f117a30bc978e649ecc8421a48fb933e7e4ae95 (patch) | |
tree | 80df6783b57c7eaa30eafe4cd7a5a3efb3cba656 /src/Test/VeriFuzz | |
parent | 2b233030e58051bae4185e5b46522543cdf56e44 (diff) | |
download | verismith-5f117a30bc978e649ecc8421a48fb933e7e4ae95.tar.gz verismith-5f117a30bc978e649ecc8421a48fb933e7e4ae95.zip |
Type fixes
Diffstat (limited to 'src/Test/VeriFuzz')
-rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index d3e6ea5..b5fb944 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -35,11 +35,12 @@ fromGate Xor = BinXor genPortsAST :: Circuit -> [Port] genPortsAST c = - (Port Input . frNode <$> inp) ++ (Port Output . frNode <$> out) + (port Input . frNode <$> inp) ++ (port Output . frNode <$> out) where inp = inputs graph out = outputs graph graph = getCircuit c + port x = Port (Just x) Nothing -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -54,25 +55,25 @@ genAssignExpr g (n:ns) = OpExpr wire op <$> genAssignExpr g ns -- | Generate the continuous assignment AST for a particular node. If it does -- not have any nodes that link to it then return 'Nothing', as that means that -- the assignment will just be empty. -genContAssignAST :: Circuit -> LNode Gate -> Maybe ContAssign -genContAssignAST c (n, g) = ContAssign name <$> genAssignExpr g nodes +genContAssignAST :: Circuit -> LNode Gate -> Maybe ModItem +genContAssignAST c (n, g) = ModCA . ContAssign name <$> genAssignExpr g nodes where gr = getCircuit c nodes = G.pre gr n name = frNode n -genAssignAST :: Circuit -> [ContAssign] +genAssignAST :: Circuit -> [ModItem] genAssignAST c = catMaybes $ genContAssignAST c <$> nodes where gr = getCircuit c nodes = G.labNodes gr -genModuleDeclAST :: Circuit -> ModuleDecl -genModuleDeclAST c = ModuleDecl id ports items +genModuleDeclAST :: Circuit -> ModDecl +genModuleDeclAST c = ModDecl id ports items where id = Identifier "gen_module" ports = genPortsAST c - items = Assign <$> genAssignAST c + items = genAssignAST c generateAST :: Circuit -> SourceText generateAST c = SourceText [Description $ genModuleDeclAST c] |