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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 15:11:52 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 15:11:52 +0000 |
commit | 9b3405316b630fc96d6c4980c7f227c1fd005e6e (patch) | |
tree | 9c47d7744ffe10625d8869f5ec0ba7a69ca2929c /src/Test/VeriFuzz | |
parent | 282cb4c4352e87f3e971d116bd6c7fa2c64fb284 (diff) | |
download | verismith-9b3405316b630fc96d6c4980c7f227c1fd005e6e.tar.gz verismith-9b3405316b630fc96d6c4980c7f227c1fd005e6e.zip |
Fix data types and apply more hlint suggestions
Diffstat (limited to 'src/Test/VeriFuzz')
-rw-r--r-- | src/Test/VeriFuzz/VerilogAST.hs | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs index 53efad1..109f024 100644 --- a/src/Test/VeriFuzz/VerilogAST.hs +++ b/src/Test/VeriFuzz/VerilogAST.hs @@ -63,14 +63,14 @@ data Port = Port { _portName :: Identifier } deriving (Show) makeLenses ''Port -data ModuleItem = Assign ContAssign +newtype ModuleItem = Assign ContAssign deriving (Show) makeLenses ''ModuleItem -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' -data ModuleDecl = ModuleDecl { _moduleId :: Identifier - , _modPorts :: [Port] - , _moduleItem :: ModuleItem +data ModuleDecl = ModuleDecl { _moduleId :: Identifier + , _modPorts :: [Port] + , _moduleItems :: [ModuleItem] } deriving (Show) makeLenses ''ModuleDecl @@ -86,9 +86,7 @@ numExpr :: Int -> Int -> Expression numExpr = ((PrimExpr . PrimNum) .) . Number emptyMod :: ModuleDecl -emptyMod = - ModuleDecl (Identifier "") [] $ Assign $ ContAssign (Identifier "") $ - OpExpr (numExpr 32 0) BinAnd (numExpr 32 0) +emptyMod = ModuleDecl (Identifier "") [] [] setModName :: Text -> ModuleDecl -> ModuleDecl -setModName str = moduleId .~ (Identifier str) +setModName str = moduleId .~ Identifier str |