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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-09 21:37:29 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-09 21:37:29 +0000 |
commit | e5a7cfbaeaac6a5f9ca9a7cd9883cf788417681a (patch) | |
tree | 4458cae2b052c73fa158c1f0dddc3f98f6687bbc /src/Test | |
parent | 8e4e3c6bfdb6a34650646cbc2330377771b74313 (diff) | |
download | verismith-e5a7cfbaeaac6a5f9ca9a7cd9883cf788417681a.tar.gz verismith-e5a7cfbaeaac6a5f9ca9a7cd9883cf788417681a.zip |
Generate some Verilog code from graph
Diffstat (limited to 'src/Test')
-rw-r--r-- | src/Test/VeriFuzz/CodeGen.hs | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs index 3965b16..6cf2d27 100644 --- a/src/Test/VeriFuzz/CodeGen.hs +++ b/src/Test/VeriFuzz/CodeGen.hs @@ -1 +1,33 @@ +{-# LANGUAGE OverloadedStrings #-} + module Test.VeriFuzz.CodeGen where + +import Data.Text (Text, empty, pack) +import Data.Graph.Inductive (Graph, Node, indeg, outdeg, nodes) + +import Test.VeriFuzz.Types + +fromNode :: Node -> Text +fromNode node = pack $ "w" <> show node + +filterGr :: (Graph gr) => gr n e -> (Node -> Bool) -> [Node] +filterGr graph f = + filter f $ nodes graph + +generate :: (Graph gr) => gr Gate e -> Text +generate graph = + "module generated_module(\n" + <> fromList (imap " " ",\n" inp) + <> fromList (imap " " ",\n" out) + <> ");\n" + <> fromList (imap " input wire " ";\n" inp) + <> fromList (imap " output wire " ";\n" out) + <> "endmodule\n" + where + and a b c = a == b && a /= c + inputs n = indeg graph n == 0 && outdeg graph n /= 0 + outputs n = indeg graph n /= 0 && outdeg graph n == 0 + fromList = foldl mappend empty + inp = filterGr graph inputs + out = filterGr graph outputs + imap b e = map ((\s -> b <> s <> e) . fromNode) |